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authorVikas Manocha <vikas.manocha@st.com>2015-07-02 18:29:43 -0700
committerJagan Teki <jteki@openedev.com>2015-07-03 13:50:53 +0530
commitc0535c0ef0b7e7a3e4c1011266bf26baf94fd4a3 (patch)
treeffa0ce2c9717d78de86cb47bd0ca32f0522712e0
parent51d558392bc71f9cfb58ce5ea70975dee6bf6292 (diff)
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spi: cadence_qspi: move the sram partition in init
There is no need to re-configure sram partition for every read/write for better full use of sram for read or write. This patch divides the half sram for read & half for write once at initialization. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Tested-by: Stefan Roese <sr@denx.de> Reviewed-by: Jagannadh Teki <jteki@openedev.com>
-rw-r--r--drivers/spi/cadence_qspi_apb.c16
1 files changed, 5 insertions, 11 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index 00a115f..fb78892 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -38,10 +38,7 @@
/* Controller sram size in word */
#define CQSPI_REG_SRAM_SIZE_WORD (128)
-#define CQSPI_REG_SRAM_RESV_WORDS (2)
-#define CQSPI_REG_SRAM_PARTITION_WR (1)
-#define CQSPI_REG_SRAM_PARTITION_RD \
- (CQSPI_REG_SRAM_SIZE_WORD - CQSPI_REG_SRAM_RESV_WORDS)
+#define CQSPI_REG_SRAM_PARTITION_RD (CQSPI_REG_SRAM_SIZE_WORD/2)
#define CQSPI_REG_SRAM_THRESHOLD_WORDS (50)
/* Transfer mode */
@@ -538,6 +535,10 @@ void cadence_qspi_apb_controller_init(struct cadence_spi_platdata *plat)
/* Configure the remap address register, no remap */
writel(0, plat->regbase + CQSPI_REG_REMAP);
+ /* Indirect mode configurations */
+ writel(CQSPI_REG_SRAM_PARTITION_RD,
+ plat->regbase + CQSPI_REG_SRAMPARTITION);
+
/* Disable all interrupts */
writel(0, plat->regbase + CQSPI_REG_IRQMASK);
@@ -700,10 +701,6 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
- /* Configure SRAM partition for read. */
- writel(CQSPI_REG_SRAM_PARTITION_RD, plat->regbase +
- CQSPI_REG_SRAMPARTITION);
-
/* Configure the opcode */
rd_reg = cmdbuf[0] << CQSPI_REG_RD_INSTR_OPCODE_LSB;
@@ -801,9 +798,6 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
writel(((u32)plat->ahbbase & CQSPI_INDIRECTTRIGGER_ADDR_MASK),
plat->regbase + CQSPI_REG_INDIRECTTRIGGER);
- writel(CQSPI_REG_SRAM_PARTITION_WR,
- plat->regbase + CQSPI_REG_SRAMPARTITION);
-
/* Configure the opcode */
reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);