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authorWolfgang Denk <wd@denx.de>2010-09-15 22:06:32 +0200
committerWolfgang Denk <wd@denx.de>2010-09-15 22:06:32 +0200
commita12555c02d716f62aa1ec4764cf1c42bfeecf07d (patch)
tree5ba47ef29f64294150f41461b823b8108bb15554
parente6060a7f18c989e0839b3d715f80bcf33de5b583 (diff)
parent1075b07e2c67c1f504d9f3a6f1b9aaa8f81393b2 (diff)
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Merge branch 'master' of git://git.denx.de/u-boot-nand-flash
-rw-r--r--drivers/mtd/nand/davinci_nand.c15
1 files changed, 14 insertions, 1 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index 4ca738e..c5a86d6 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -484,7 +484,20 @@ static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
__raw_writel(1 << 13, &davinci_emif_regs->nandfcr);
/*
- * Wait for the corr_state field (bits 8 to 11)in the
+ * Wait for the corr_state field (bits 8 to 11) in the
+ * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
+ * Otherwise ECC calculation has not even begun and the next loop might
+ * fail because of a false positive!
+ */
+ i = NAND_TIMEOUT;
+ do {
+ val = __raw_readl(&davinci_emif_regs->nandfsr);
+ val &= 0xc00;
+ i--;
+ } while ((i > 0) && !val);
+
+ /*
+ * Wait for the corr_state field (bits 8 to 11) in the
* NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
*/
i = NAND_TIMEOUT;