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authorMarek Vasut <marex@denx.de>2014-09-15 01:27:57 +0200
committerMarek Vasut <marex@denx.de>2014-10-06 17:46:50 +0200
commit9ca2116ce49449602eb9e2f8a0cafe811bcc3086 (patch)
tree61cd055ff4710141c57d53e2d574c433a5176b7d
parent807abb18f1376bcd674540e374f2ab7503caea51 (diff)
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arm: socfpga: cache: Define cacheline size
The Cortex-A9 has 32-byte long L1 cachelines. Define this value. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
-rw-r--r--include/configs/socfpga_cyclone5.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index 54343b8..76979b1 100644
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -26,6 +26,8 @@
#define CONFIG_SOCFPGA
#define CONFIG_CLOCKS
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
/* base address for .text section */
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_SYS_TEXT_BASE 0x08000040