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authorStefan Roese <sr@denx.de>2016-03-03 16:57:39 +0100
committerMarek Vasut <marex@denx.de>2016-03-20 18:01:11 +0100
commit93d9fc26cb7b4fcbb849e79d21d16b114e4501a9 (patch)
treee05bbc0acde8776bdd2566c03e7206e726d881c5
parentead2fb29e8fc3752e844d5ff4f9e668b42a4e744 (diff)
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arm: socfpga: sr1500: Misc updates (SPI speed, env location)
This patch makes the following changes to the SR1500 board port: - Update defconfig to support SPI NOR (use make savedefconfig). - Increase SPI speed to a maximum of 100MHz for faster system bootup. - Change environment location, so that its not between SPL and main U-Boot. This way the combined SPL / U-Boot image can be used for updates. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de>
-rw-r--r--arch/arm/dts/socfpga_cyclone5_sr1500.dts2
-rw-r--r--configs/socfpga_sr1500_defconfig2
-rw-r--r--include/configs/socfpga_sr1500.h19
3 files changed, 15 insertions, 8 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_sr1500.dts b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
index 3729ca0..32c6aad 100644
--- a/arch/arm/dts/socfpga_cyclone5_sr1500.dts
+++ b/arch/arm/dts/socfpga_cyclone5_sr1500.dts
@@ -88,7 +88,7 @@
#size-cells = <1>;
compatible = "n25q00", "spi-flash";
reg = <0>; /* chip select */
- spi-max-frequency = <50000000>;
+ spi-max-frequency = <100000000>;
m25p,fast-read;
page-size = <256>;
block-size = <16>; /* 2^16, 64KB */
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 59a6be4..d499a14 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -15,7 +15,9 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DWAPB_GPIO=y
CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_DM_ETH=y
CONFIG_ETH_DESIGNWARE=y
CONFIG_SYS_NS16550=y
+CONFIG_CADENCE_QSPI=y
diff --git a/include/configs/socfpga_sr1500.h b/include/configs/socfpga_sr1500.h
index e4aafaa..6414eeb 100644
--- a/include/configs/socfpga_sr1500.h
+++ b/include/configs/socfpga_sr1500.h
@@ -93,22 +93,27 @@
#define CONFIG_SYS_BOOTCOUNT_BE
/* Environment setting for SPI flash */
-#undef CONFIG_ENV_SIZE
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE (16 * 1024)
-#define CONFIG_ENV_OFFSET 0x00040000
+#define CONFIG_ENV_OFFSET 0x000e0000
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MODE SPI_MODE_3
-#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
+#define CONFIG_ENV_SPI_MAX_HZ 100000000 /* Use max of 100MHz */
+#define CONFIG_SF_DEFAULT_SPEED 100000000
+
+/*
+ * The QSPI NOR flash layout on SR1500:
+ *
+ * 0000.0000 - 0003.ffff: SPL (4 times)
+ * 0004.0000 - 000d.ffff: U-Boot
+ * 000e.0000 - 000e.ffff: env1
+ * 000f.0000 - 000f.ffff: env2
+ */
/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>
-/* U-Boot payload is stored at offset 0x60000 */
-#undef CONFIG_SYS_SPI_U_BOOT_OFFS
-#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
-
#endif /* __CONFIG_SOCFPGA_SR1500_H__ */