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authorMichal Simek <michal.simek@xilinx.com>2014-01-21 07:29:47 +0100
committerMichal Simek <michal.simek@xilinx.com>2014-02-04 16:48:57 +0100
commit8c3bd6b596300d0ade265329f44832e89ef54a22 (patch)
tree65a9ba250384539ce17006498974a2e38ad753ff
parentb44bd2c73c4cfb6e3b9e7f8cf987e8e39aa74a0b (diff)
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serial: uartlite: Reset RX/TX in init
Just to be sure that there is no pending data. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--drivers/serial/serial_xuartlite.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/serial/serial_xuartlite.c b/drivers/serial/serial_xuartlite.c
index e613994..988438e 100644
--- a/drivers/serial/serial_xuartlite.c
+++ b/drivers/serial/serial_xuartlite.c
@@ -18,10 +18,14 @@
#define SR_RX_FIFO_VALID_DATA 0x01 /* data in receive FIFO */
#define SR_RX_FIFO_FULL 0x02 /* receive FIFO full */
+#define ULITE_CONTROL_RST_TX 0x01
+#define ULITE_CONTROL_RST_RX 0x02
+
struct uartlite {
unsigned int rx_fifo;
unsigned int tx_fifo;
unsigned int status;
+ unsigned int control;
};
static struct uartlite *userial_ports[4] = {
@@ -75,8 +79,16 @@ static int uartlite_serial_tstc(const int port)
static int uartlite_serial_init(const int port)
{
- if (userial_ports[port])
+ struct uartlite *regs = userial_ports[port];
+
+ if (regs) {
+ out_be32(&regs->control, 0);
+ out_be32(&regs->control,
+ ULITE_CONTROL_RST_RX | ULITE_CONTROL_RST_TX);
+ in_be32(&regs->control);
return 0;
+ }
+
return -1;
}