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authorMarek Vasut <marex@denx.de>2014-04-28 03:38:41 +0200
committerStefano Babic <sbabic@denx.de>2014-09-29 09:02:16 +0200
commit7c604e98c2213619af6a8c3064418af9b689cf56 (patch)
tree0136e43f6868659a79c5cfb47004f47e975b5f5e
parentbe0ecdbed5efc7833275701ebdb1ff8ef7ffd4c0 (diff)
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arm: mxs: Wait for DRAM to start
Instead of waiting for a fixed period of time and hoping for the best that the DRAM will start, read back an EMI status register which tells us exactly when the DRAM started. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
-rw-r--r--arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c8
1 files changed, 7 insertions, 1 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index de8841a..97ef67d 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -274,7 +274,13 @@ static void mx23_mem_init(void)
setbits_le32(MXS_DRAM_BASE + 0x20, 1 << 16);
clrbits_le32(MXS_DRAM_BASE + 0x40, 1 << 17);
- early_delay(20000);
+
+ /* Wait for EMI_STAT bit DRAM_HALTED */
+ for (;;) {
+ if (!(readl(MXS_EMI_BASE + 0x10) & (1 << 1)))
+ break;
+ early_delay(1000);
+ }
/* Adjust EMI port priority. */
clrsetbits_le32(0x80020000, 0x1f << 16, 0x2);