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authorKumar Gala <galak@kernel.crashing.org>2006-02-22 14:15:41 -0600
committerKumar Gala <galak@kernel.crashing.org>2006-02-22 14:15:41 -0600
commit79582020313e6d992a3bac71cf3a9b337f9ac7f7 (patch)
tree5eefe0c7b244ffd0798e64f9a83ec7084032a816
parent230b31febf39f9d9f19679cf0112d9e30415122d (diff)
parent6624b687bc2b747233090e67628df37d1c84ed17 (diff)
downloadu-boot-imx-79582020313e6d992a3bac71cf3a9b337f9ac7f7.zip
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Merge rsync://rsync.denx.de/git/u-boot
-rw-r--r--CHANGELOG55
-rw-r--r--Makefile35
-rw-r--r--board/amirix/ap1000/ap1000.c10
-rw-r--r--board/esd/cms700/cms700.c2
-rw-r--r--board/esd/common/auto_update.c2
-rw-r--r--board/esd/common/cmd_loadpci.c123
-rw-r--r--board/esd/common/lcd.c3
-rw-r--r--board/esd/cpci2dp/Makefile2
-rw-r--r--board/esd/cpci2dp/cpci2dp.c32
-rw-r--r--board/esd/cpci750/Makefile2
-rw-r--r--board/esd/cpci750/cpci750.c17
-rw-r--r--board/esd/cpci750/pci.c80
-rw-r--r--board/esd/cpci750/strataflash.c763
-rw-r--r--board/esd/hh405/fpgadata.c5037
-rw-r--r--board/esd/hh405/hh405.c143
-rw-r--r--board/esd/pmc405/Makefile2
-rw-r--r--board/esd/pmc405/pmc405.c81
-rw-r--r--board/esd/vom405/vom405.c2
-rw-r--r--board/pm520/flash.c9
-rw-r--r--board/xilinx/xilinx_enet/emac_adapter.c2
-rw-r--r--cpu/ppc4xx/405gp_pci.c9
-rw-r--r--drivers/ct69000.c21
-rw-r--r--drivers/i8042.c19
-rw-r--r--fs/ext2/ext2fs.c2
-rw-r--r--include/configs/CPCI2DP.h10
-rw-r--r--include/configs/CPCI405.h4
-rw-r--r--include/configs/CPCI4052.h4
-rw-r--r--include/configs/CPCI405AB.h4
-rw-r--r--include/configs/CPCI405DT.h4
-rw-r--r--include/configs/CPCI750.h30
-rw-r--r--include/configs/HH405.h15
-rw-r--r--include/configs/PM520.h4
-rw-r--r--include/configs/PMC405.h42
-rw-r--r--include/configs/inka4x0.h30
-rw-r--r--include/configs/smmaco4.h373
-rw-r--r--include/pci_ids.h1
-rw-r--r--include/version.h4
-rw-r--r--lib_arm/board.c57
-rw-r--r--tools/mkimage.c2
-rwxr-xr-xtools/setlocalversion22
40 files changed, 3597 insertions, 3462 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 5a1ef9f..eaa1893 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -73,7 +73,60 @@ Changes since U-Boot 1.1.4:
* Added PCI support for MPC8349ADS board
Patch by Kumar Gala 11 Jan 2006
-* Add support for 28F256J3A flah (=> 64 MB) on PM520 board
+* Add basic support for the SMMACO4 Board from PanDaCom.
+ Patch by Heiko Schocher, 20 Feb 2006
+
+* Add GIT version information (commid ID) to untagged U-Boot versions
+
+ As done in the linux kernel, the U-Boot version (U_BOOT_VERSION)
+ of all unreleased (untagged) U-Boot images will be automatically
+ extended upon compiletime with a part of the GIT commit ID and
+ possibly with "dirty" if uncommited changes are detected.
+
+ Here an example for the resulting version:
+ "U-Boot 1.1.4-g3457ac18-dirty"
+
+ The version is now maintained in the toplevel Makefile and the
+ version headers are autogenerated.
+
+ Patch by Stefan Roese, 9 Feb 2006
+
+* Update default environment for INKA4x00 board.
+
+* Convert CPCI750 to use common CFI flash driver
+ Patch by Reinhard Arlt, 8 Feb 2006
+
+* Various changes to esd HH405 board specific files
+ Patch by Matthias Fuchs, 07 Feb 2006
+
+* Cleanup U-Boot boot messages on ARM.
+
+ To match the U-Boot user interface on ARM platforms to the U-Boot
+ standard (as on PPC platforms), some messages with debug character
+ are removed from the default U-Boot build.
+ Enable DEBUG for lib_arm/board.c to enable debug messages.
+ New CONFIG_DISPLAY_CPUINFO and CONFIG_DISPLAY_BOARDINFO options.
+ Patch by Stefan Roese, 24 Jan 2006
+
+* Fix various compiler warnings on ppc4xx builds (ELDK 4.0)
+ Patch by Stefan Roese, 18 Jan 2006
+
+* Add VGA support (CT69000) to CPCI750 board.
+ Insert missing __le32_to_cpu() for filesize in ext2fs_read_file().
+ Patch by Reinhard Arlt, 30 Dec 2005
+
+* PMC405 and CPCI405: Moved configuration of pci resources
+ into config file.
+ PMC405 and CPCI2DP: Added firmware download and booting via pci.
+ Patch by Matthias Fuchs, 20 Dec 2005
+
+* Fix 28F256J3A support on PM520 board
+ (without bank-switching only 32 MB can be accessed)
+
+* Fix mkimage bug with multifile images created on 64 bit systems.
+
+* Add support for 28F256J3A flash (=> 64 MB) on PM520 board
+>>>>>>> 6624b687bc2b747233090e67628df37d1c84ed17/CHANGELOG
* Fix compiler problem with at91rm9200dk board.
Patch by Eugen Bigz, 19 Dec 2005
diff --git a/Makefile b/Makefile
index 9305cab..8349176 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
#
-# (C) Copyright 2000-2005
+# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@@ -21,6 +21,13 @@
# MA 02111-1307 USA
#
+VERSION = 1
+PATCHLEVEL = 1
+SUBLEVEL = 4
+EXTRAVERSION =
+U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
+VERSION_FILE = include/version_autogenerated.h
+
HOSTARCH := $(shell uname -m | \
sed -e s/i.86/i386/ \
-e s/sun4u/sparc64/ \
@@ -154,14 +161,14 @@ u-boot.bin: u-boot
u-boot.img: u-boot.bin
./tools/mkimage -A $(ARCH) -T firmware -C none \
-a $(TEXT_BASE) -e 0 \
- -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' include/version.h | \
+ -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
-d $< $@
u-boot.dis: u-boot
$(OBJDUMP) -d $< > $@
-u-boot: depend $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
+u-boot: depend version $(SUBDIRS) $(OBJS) $(LIBS) $(LDSCRIPT)
UNDEF_SYM=`$(OBJDUMP) -x $(LIBS) |sed -n -e 's/.*\(__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
$(LD) $(LDFLAGS) $$UNDEF_SYM $(OBJS) \
--start-group $(LIBS) --end-group $(PLATFORM_LIBS) \
@@ -173,6 +180,13 @@ $(LIBS):
$(SUBDIRS):
$(MAKE) -C $@ all
+version:
+ @echo -n "#define U_BOOT_VERSION \"U-Boot " > $(VERSION_FILE); \
+ echo -n "$(U_BOOT_VERSION)" >> $(VERSION_FILE); \
+ echo -n $(shell $(CONFIG_SHELL) $(TOPDIR)/tools/setlocalversion \
+ $(TOPDIR)) >> $(VERSION_FILE); \
+ echo "\"" >> $(VERSION_FILE)
+
gdbtools:
$(MAKE) -C tools/gdb || exit 1
@@ -301,6 +315,14 @@ PM520_ROMBOOT_DDR_config: unconfig
}
@./mkconfig -a PM520 ppc mpc5xxx pm520
+smmaco4_config: unconfig
+ @./mkconfig -a smmaco4 ppc mpc5xxx tqm5200
+
+spieval_config: unconfig
+ echo "#define CONFIG_CS_AUTOCONF">>include/config.h
+ echo "... with automatic CS configuration"
+ @./mkconfig -a spieval ppc mpc5xxx tqm5200
+
MINI5200_config \
EVAL5200_config \
TOP5200_config: unconfig
@@ -366,11 +388,6 @@ MiniFAP_config: unconfig
}
@./mkconfig -a TQM5200 ppc mpc5xxx tqm5200
-spieval_config: unconfig
- echo "#define CONFIG_CS_AUTOCONF">>include/config.h
- echo "... with automatic CS configuration"
- @./mkconfig -a spieval ppc mpc5xxx tqm5200
-
#########################################################################
## MPC8xx Systems
#########################################################################
@@ -1838,7 +1855,7 @@ clobber: clean
-o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \
-print0 \
| xargs -0 rm -f
- rm -f $(OBJS) *.bak tags TAGS
+ rm -f $(OBJS) *.bak tags TAGS include/version_autogenerated.h
rm -fr *.*~
rm -f u-boot u-boot.map u-boot.hex $(ALL)
rm -f tools/crc32.c tools/environment.c tools/env/crc32.c
diff --git a/board/amirix/ap1000/ap1000.c b/board/amirix/ap1000/ap1000.c
index dd836ce..7d11b29 100644
--- a/board/amirix/ap1000/ap1000.c
+++ b/board/amirix/ap1000/ap1000.c
@@ -36,8 +36,8 @@ int board_pre_init (void)
/** serial number and platform display at startup */
int checkboard (void)
{
- unsigned char *s = getenv ("serial#");
- unsigned char *e;
+ char *s = getenv ("serial#");
+ char *e;
/* After a loadace command, the SystemAce control register is left in a wonky state. */
/* this code did not work in board_pre_init */
@@ -135,13 +135,13 @@ int checkboard (void)
long int initdram (int board_type)
{
- unsigned char *s = getenv ("dramsize");
+ char *s = getenv ("dramsize");
if (s != NULL) {
if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
s += 2;
}
- return simple_strtoul (s, NULL, 16);
+ return (long int)simple_strtoul (s, NULL, 16);
} else {
/* give all 64 MB */
return 64 * 1024 * 1024;
@@ -293,7 +293,7 @@ int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
printf ("Writing to Flash... ");
write_result =
- flash_write (sector_buffer, SW_BYTE_SECTOR_ADDR,
+ flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR,
SW_BYTE_SECTOR_SIZE);
if (write_result != 0) {
flash_perror (write_result);
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 649619d..e4cfe14 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -114,7 +114,7 @@ int misc_init_r (void)
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int flashcnt;
int delay;
volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index d48e972..1decc0e 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -283,7 +283,7 @@ int au_do_update(int i, long sz)
*/
if (au_image[i].type != AU_NAND) {
debug ("flash_write(%p, %lx %x)\n", addr, start, nbytes);
- rc = flash_write((uchar *)addr, start, nbytes);
+ rc = flash_write((char *)addr, start, nbytes);
} else {
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
debug ("nand_rw(%p, %lx %x)\n", addr, start, nbytes);
diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c
new file mode 100644
index 0000000..3478f82
--- /dev/null
+++ b/board/esd/common/cmd_loadpci.c
@@ -0,0 +1,123 @@
+/*
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd GmbH Germany, matthias.fuchs@esd-electronics.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_BSP)
+
+extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
+extern int do_autoscript (cmd_tbl_t *, int, int, char *[]);
+
+#define ADDRMASK 0xfffff000
+
+/*
+ * Command loadpci: wait for signal from host and boot image.
+ */
+int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ unsigned int *ptr = 0;
+ int count = 0;
+ int count2 = 0;
+ char addr[16];
+ char str[] = "\\|/-";
+ char *local_args[2];
+
+ while(1) {
+ /*
+ * Mark sync address
+ */
+ ptr = 0;
+ memset(ptr, 0, 0x20);
+
+ *ptr = 0xffffffff;
+ puts("\nWaiting for action from pci host -");
+
+ /*
+ * Wait for host to write the start address
+ */
+ while (*ptr == 0xffffffff) {
+ count++;
+ if (!(count % 100)) {
+ count2++;
+ putc(0x08); /* backspace */
+ putc(str[count2 % 4]);
+ }
+
+ /* Abort if ctrl-c was pressed */
+ if (ctrlc()) {
+ puts("\nAbort\n");
+ return 0;
+ }
+
+ udelay(1000);
+ }
+
+ printf("\nGot bootcode %08x: ", *ptr);
+ sprintf(addr, "%08x", *ptr & ADDRMASK);
+
+ switch (*ptr & ~ADDRMASK) {
+ case 0:
+ /*
+ * Boot image via bootm
+ */
+ printf("booting image at addr 0x%s ...\n", addr);
+ setenv("loadaddr", addr);
+
+ do_bootm (cmdtp, 0, 0, NULL);
+ break;
+
+ case 1:
+ /*
+ * Boot image via autoscr
+ */
+ printf("executing script at addr 0x%s ...\n", addr);
+
+ local_args[0] = addr;
+ local_args[1] = NULL;
+ do_autoscript(cmdtp, 0, 1, local_args);
+ break;
+
+ case 2:
+ /*
+ * Call run_cmd
+ */
+ printf("running command at addr 0x%s ...\n", addr);
+ run_command ((char*)(*ptr & ADDRMASK), 0);
+ break;
+
+ default:
+ printf("unhandled boot method\n");
+ break;
+ }
+ }
+}
+
+U_BOOT_CMD(
+ loadpci, 1, 1, do_loadpci,
+ "loadpci - Wait for pci bootcmd and boot it\n",
+ NULL
+ );
+
+#endif
+
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index 0edc083..196171c 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -229,6 +229,9 @@ void lcd_init(uchar *lcd_reg, uchar *lcd_mem, S1D_REGS *regs, int reg_count,
/*
* Detect epson
*/
+ lcd_reg[0] = 0x00;
+ lcd_reg[1] = 0x00;
+
if (lcd_reg[0] == 0x1c) {
/*
* Big epson detected
diff --git a/board/esd/cpci2dp/Makefile b/board/esd/cpci2dp/Makefile
index a60495a..88b0ae3 100644
--- a/board/esd/cpci2dp/Makefile
+++ b/board/esd/cpci2dp/Makefile
@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
-OBJS = $(BOARD).o flash.o ../common/misc.o
+OBJS = $(BOARD).o flash.o ../common/misc.o ../common/cmd_loadpci.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index df10c0e..2800420 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -31,17 +31,15 @@ int board_early_init_f (void)
unsigned long cntrl0Reg;
/*
- * Setup GPIO pins (CS4+CS7 as GPIO)
+ * Setup GPIO pins
*/
cntrl0Reg = mfdcr(cntrl0);
- mtdcr(cntrl0, cntrl0Reg | 0x00900000);
+ mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
- /* set output pins to high */
- out32(GPIO0_OR, CFG_INTA_FAKE | CFG_EEPROM_WP | CFG_PB_LED);
- /* INTA# is open drain */
- out32(GPIO0_ODR, CFG_INTA_FAKE);
- /* setup for output */
- out32(GPIO0_TCR, CFG_INTA_FAKE | CFG_EEPROM_WP);
+ /* set output pins to high */
+ out32(GPIO0_OR, CFG_EEPROM_WP);
+ /* setup for output (LED=off) */
+ out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
/*
* IRQ 0-15 405GP internally generated; active high; level sensitive
@@ -130,16 +128,6 @@ long int initdram (int board_type)
/* ------------------------------------------------------------------------- */
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 64 MB - ok\n");
-
- return (0);
-}
-
-/* ------------------------------------------------------------------------- */
-
#if defined(CFG_EEPROM_WREN)
/* Input: <dev_addr> I2C address of EEPROM device to enable.
* <state> -1: deliver current state
@@ -207,8 +195,8 @@ int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
U_BOOT_CMD(
- eepwren, 2, 0, do_eep_wren,
- "eepwren - Enable / disable / query EEPROM write access\n",
- NULL
- );
+ eepwren, 2, 0, do_eep_wren,
+ "eepwren - Enable / disable / query EEPROM write access\n",
+ NULL
+ );
#endif /* #if defined(CFG_EEPROM_WREN) */
diff --git a/board/esd/cpci750/Makefile b/board/esd/cpci750/Makefile
index 0486729..cd38b2d 100644
--- a/board/esd/cpci750/Makefile
+++ b/board/esd/cpci750/Makefile
@@ -29,7 +29,7 @@ SOBJS = misc.o
OBJS = $(BOARD).o serial.o ../../Marvell/common/memory.o pci.o \
mv_eth.o mpsc.o i2c.o \
- sdram_init.o strataflash.o ide.o
+ sdram_init.o ide.o
$(LIB): .depend $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(SOBJS)
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index e4b062b..fd0f904 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -56,6 +56,7 @@
extern void flush_data_cache (void);
extern void invalidate_l1_instruction_cache (void);
+extern flash_info_t flash_info[];
/* ------------------------------------------------------------------------- */
@@ -363,6 +364,22 @@ int misc_init_r ()
/* disable the dcache and MMU */
dcache_lock ();
#endif
+ if (flash_info[3].size < CFG_FLASH_INCREMENT) {
+ unsigned int flash_offset;
+ unsigned int l;
+
+ flash_offset = CFG_FLASH_INCREMENT - flash_info[3].size;
+ for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
+ if (flash_info[3].start[l] != 0) {
+ flash_info[3].start[l] += flash_offset;
+ }
+ }
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_MONITOR_BASE,
+ CFG_MONITOR_BASE + monitor_flash_len - 1,
+ &flash_info[3]);
+
+ }
return 0;
}
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index 3e44fb9..37c7150 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -44,6 +44,14 @@ static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
{0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
};
+#ifdef CONFIG_USE_CPCIDVI
+typedef struct {
+ unsigned int base;
+ unsigned int init;
+} GT_CPCIDVI_ROM_T;
+
+static GT_CPCIDVI_ROM_T gt_cpcidvi_rom = {0, 0};
+#endif
#ifdef DEBUG
static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
@@ -800,21 +808,63 @@ static void gt_setup_ide (struct pci_controller *hose,
unsigned int offset =
(bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- 0x0);
- pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
- &bar_response);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+ 0x0);
+ pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + offset,
+ &bar_response);
pciauto_region_allocate (bar_response &
PCI_BASE_ADDRESS_SPACE_IO ? hose->
pci_io : hose->pci_mem, ide_bar[bar],
&bar_value);
- pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
- bar_value);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0 + bar * 4,
+ bar_value);
}
}
+#ifdef CONFIG_USE_CPCIDVI
+static void gt_setup_cpcidvi (struct pci_controller *hose,
+ pci_dev_t dev, struct pci_config_table *entry)
+{
+ u32 bar_value, pci_response;
+
+ pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &pci_response);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, 0xffffffff);
+ pci_hose_read_config_dword (hose, dev, PCI_BASE_ADDRESS_0, &pci_response);
+ pciauto_region_allocate (hose->pci_mem, 0x01000000, &bar_value);
+ pci_hose_write_config_dword (hose, dev, PCI_BASE_ADDRESS_0, (bar_value & 0xffffff00));
+ pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, 0x0);
+ pciauto_region_allocate (hose->pci_mem, 0x40000, &bar_value);
+ pci_hose_write_config_dword (hose, dev, PCI_ROM_ADDRESS, (bar_value & 0xffffff00) | 0x01);
+ gt_cpcidvi_rom.base = bar_value & 0xffffff00;
+ gt_cpcidvi_rom.init = 1;
+}
+
+unsigned char gt_cpcidvi_in8(unsigned int offset)
+{
+ unsigned char data;
+
+ if (gt_cpcidvi_rom.init == 0) {
+ return(0);
+ }
+ data = in8((offset & 0x04) + 0x3f000 + gt_cpcidvi_rom.base);
+ return(data);
+}
+
+void gt_cpcidvi_out8(unsigned int offset, unsigned char data)
+{
+ unsigned int off;
+
+ if (gt_cpcidvi_rom.init == 0) {
+ return;
+ }
+ off = data;
+ off = ((off << 3) & 0x7f8) + (offset & 0x4) + 0x3e000 + gt_cpcidvi_rom.base;
+ in8(off);
+ return;
+}
+#endif
/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
/* and is curently not called *. */
@@ -835,9 +885,12 @@ static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
#endif
struct pci_config_table gt_config_table[] = {
+#ifdef CONFIG_USE_CPCIDVI
+ {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030, PCI_CLASS_DISPLAY_VGA,
+ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_cpcidvi},
+#endif
{PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
-
{}
};
@@ -857,10 +910,21 @@ void pci_init_board (void)
#ifdef CONFIG_PCI_PNP
unsigned int bar;
#endif
-
#ifdef DEBUG
gt_pci_bus_mode_display (PCI_HOST0);
#endif
+#ifdef CONFIG_USE_CPCIDVI
+ gt_cpcidvi_rom.init = 0;
+ gt_cpcidvi_rom.base = 0;
+#endif
+
+ pci0_hose.config_table = gt_config_table;
+ pci1_hose.config_table = gt_config_table;
+
+#ifdef CONFIG_USE_CPCIDVI
+ gt_config_table[0].config_device = gt_setup_cpcidvi;
+#endif
+ gt_config_table[1].config_device = gt_setup_ide;
pci0_hose.first_busno = 0;
pci0_hose.last_busno = 0xff;
diff --git a/board/esd/cpci750/strataflash.c b/board/esd/cpci750/strataflash.c
deleted file mode 100644
index c22fe5d..0000000
--- a/board/esd/cpci750/strataflash.c
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/cache.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for U-Boot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-
-#define FLASH_MAN_CFI 0x01000000
-
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char * cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c);
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf);
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd);
-static int flash_detect_cfi(flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-inline uchar * flash_make_addr(flash_info_t * info, int sect, int offset)
-{
- return ((uchar *)(info->start[sect] + (offset * info->portwidth)));
-}
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-inline uchar flash_read_uchar(flash_info_t * info, uchar offset)
-{
- uchar *cp;
- cp = flash_make_addr(info, 0, offset);
- return (cp[info->portwidth - 1]);
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ((addr[(2*info->portwidth) - 1] << 8) | addr[info->portwidth - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long(flash_info_t * info, int sect, uchar offset)
-{
- uchar * addr;
-
- addr = flash_make_addr(info, sect, offset);
- return ( (addr[(2*info->portwidth) - 1] << 24 ) | (addr[(info->portwidth) -1] << 16) |
- (addr[(4*info->portwidth) - 1] << 8) | addr[(3*info->portwidth) - 1]);
-
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
- unsigned long address;
-
-
- /* The flash is positioned back to back, with the demultiplexing of the chip
- * based on the A24 address line.
- *
- */
-
- address = CFG_FLASH_BASE;
- size = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size += flash_info[i].size = flash_get_size(address, i);
- address += CFG_FLASH_INCREMENT;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
- flash_info[0].size, flash_info[i].size<<20);
- }
- }
-
-#if 0 /* test-only */
- /* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
- for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
- (void)flash_real_protect(&flash_info[0], i, 1);
-#endif
-#endif
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if( info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd(info, sect, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sect, 0, FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd(info, sect, 0, FLASH_CMD_ERASE_CONFIRM);
-
- if(flash_full_status_check(info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf(".");
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- printf("CFI conformant FLASH (%d x %d)",
- (info->portwidth << 3 ), (info->chipwidth << 3 ));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf(" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n",
- info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n");
- printf (" %08lX%5s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for(i=0;i<aln; ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
-
- for(; (i< info->portwidth) && (cnt > 0) ; i++) {
- flash_add_byte(info, &cword, *src++);
- cnt--;
- cp++;
- }
- for(; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte(info, &cword, (*(uchar *)cp));
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
- while(cnt >= info->portwidth) {
- i = info->buffer_size > cnt? cnt: info->buffer_size;
- if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -=i;
- }
-#else
- /* handle the aligned part */
- while(cnt >= info->portwidth) {
- cword.l = 0;
- for(i = 0; i < info->portwidth; i++) {
- flash_add_byte(info, &cword, *src++);
- }
- if((rc = flash_write_cfiword(info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i=0, cp=wp; (i<info->portwidth) && (cnt>0); ++i, ++cp) {
- flash_add_byte(info, &cword, *src++);
- --cnt;
- }
- for (; i<info->portwidth; ++i, ++cp) {
- flash_add_byte(info, & cword, (*(uchar *)cp));
- }
-
- return flash_write_cfiword(info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT);
- if(prot)
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd(info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if((retcode = flash_full_status_check(info, sector, info->erase_blk_tout,
- prot?"protect":"unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if(prot == 0) {
- int i;
- for(i = 0 ; i<info->sector_count; i++) {
- if(info->protect[i])
- flash_real_protect(info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while(!flash_isset(info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer(start) > info->erase_blk_tout) {
- printf("Flash %s timeout at address %lx\n", prompt, info->start[sector]);
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt)
-{
- int retcode;
- retcode = flash_status_check(info, sector, tout, prompt);
- if((retcode == ERR_OK) && !flash_isequal(info,sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf("Flash %s error at address %lx\n", prompt,info->start[sector]);
- if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)){
- printf("Command Sequence Error.\n");
- } else if(flash_isset(info, sector, 0, FLASH_STATUS_ECLBS)){
- printf("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset(info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf("Locking Error\n");
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_DPS)){
- printf("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if(flash_isset(info, sector, 0, FLASH_STATUS_VPENS))
- printf("Vpp Low Error.\n");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte(flash_info_t *info, cfiword_t * cword, uchar c)
-{
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd(flash_info_t * info, uchar cmd, void * cmdbuf)
-{
- int i;
- uchar *cp = (uchar *)cmdbuf;
- for(i=0; i< info->portwidth; i++)
- *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd;
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
- addr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-/*-----------------------------------------------------------------------
- */
-static int flash_isset(flash_info_t * info, int sect, uchar offset, uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
- cptr.cp = flash_make_addr(info, sect, offset);
- flash_make_cmd(info, cmd, &cword);
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
- */
-static int flash_detect_cfi(flash_info_t * info)
-{
-
- for(info->portwidth=FLASH_CFI_8BIT; info->portwidth <= FLASH_CFI_32BIT;
- info->portwidth <<= 1) {
- for(info->chipwidth =FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd(info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if(flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP,'Q') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal(info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y'))
- return 1;
- }
- }
- return 0;
-}
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
- flash_info_t * info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio = 0;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-
- invalidate_dcache_range(base, base+0x400);
-
- if(flash_detect_cfi(info)){
-
- size_ratio = info->portwidth / info->chipwidth;
- num_erase_regions = flash_read_uchar(info, FLASH_OFFSET_NUM_ERASE_REGIONS);
-
- sect_cnt = 0;
- sector = base;
- for(i = 0 ; i < num_erase_regions; i++) {
- if(i > NUM_ERASE_REGIONS) {
- printf("%d erase regions found, only %d used\n",
- num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp = flash_read_long(info, 0, FLASH_OFFSET_ERASE_REGIONS);
- erase_region_size = (tmp & 0xffff)? ((tmp & 0xffff) * 256): 128;
- tmp >>= 16;
- erase_region_count = (tmp & 0xffff) +1;
- for(j = 0; j< erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] = flash_isset(info, sect_cnt, FLASH_OFFSET_PROTECT, FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size = (1 << flash_read_uchar(info, FLASH_OFFSET_SIZE)) * size_ratio;
- info->buffer_size = (1 << flash_read_ushort(info, 0, FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar(info, FLASH_OFFSET_WTOUT);
- info->write_tout = (tmp * (1 << flash_read_uchar(info, FLASH_OFFSET_WMAX_TOUT)))/ 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_RESET);
-#ifdef DEBUG_FLASH
- printf("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
-#ifdef DEBUG_FLASH
- printf("found %d erase regions\n", num_erase_regions);
-#endif
-#ifdef DEBUG_FLASH
- printf("size=%08x sectors=%08x \n", info->size, info->sector_count);
-#endif
- return(info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword)
-{
-
- cfiptr_t ctladdr;
- cfiptr_t cptr;
- int flag;
-
- ctladdr.cp = flash_make_addr(info, 0, 0);
- cptr.cp = (uchar *)dest;
-
-
- /* Check if Flash is (sufficiently) erased */
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if(!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- flash_write_cmd(info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, 0, 0, FLASH_CMD_WRITE);
-
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if(flag)
- enable_interrupts();
-
- return flash_full_status_check(info, 0, info->write_tout, "write");
-}
-
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector(flash_info_t *info, ulong addr)
-{
- int sector;
- for(sector = info->sector_count - 1; sector >= 0; sector--) {
- if(addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *)dest;
- sector = find_sector(info, dest);
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if((retcode = flash_status_check(info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd(info, sector, 0, (uchar)cnt-1);
- while(cnt-- > 0) {
- switch(info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode = flash_full_status_check(info, sector, info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/hh405/fpgadata.c b/board/esd/hh405/fpgadata.c
index 58ee3a8..64bca46 100644
--- a/board/esd/hh405/fpgadata.c
+++ b/board/esd/hh405/fpgadata.c
@@ -1,2520 +1,2517 @@
- 0x1f,0x8b,0x08,0x08,0x9c,0xc4,0xe8,0x42,0x00,0x03,0x68,0x68,0x34,0x30,0x35,0x5f,
- 0x31,0x5f,0x30,0x35,0x2e,0x62,0x69,0x74,0x00,0xec,0xfd,0x0f,0x78,0x14,0xd7,0x91,
- 0x2f,0x0c,0x57,0x9f,0x6e,0x89,0xa3,0xe9,0x91,0xa6,0x91,0x84,0x57,0xb6,0x31,0x6e,
- 0x8d,0x04,0x1e,0x94,0x91,0x18,0x46,0x58,0xc8,0x42,0x8c,0x5a,0x23,0xd9,0x19,0x1b,
- 0x6c,0x26,0x8e,0x93,0x65,0x77,0xfd,0xe5,0x0e,0x84,0x64,0x95,0xbc,0xc4,0x2b,0x3b,
- 0xb9,0x7b,0x49,0xd6,0xeb,0x1c,0x8d,0x04,0x8c,0x90,0x0c,0x03,0x28,0x31,0x4e,0x58,
- 0x6f,0x23,0x64,0x5b,0x38,0x24,0x3b,0x08,0x0c,0x02,0x1c,0xdc,0xc2,0xb2,0x2d,0xfe,
- 0x18,0x2b,0x0e,0xeb,0xe0,0x3f,0x71,0x06,0x47,0x26,0xb2,0x23,0xdb,0x32,0xc6,0x8e,
- 0x04,0x02,0xde,0x3a,0x3d,0x92,0xa6,0x47,0x64,0xf7,0xe6,0xbe,0xf7,0xf9,0xde,0x6f,
- 0x9f,0xe7,0xbb,0xf2,0xf3,0xec,0x9e,0xb4,0x8e,0x9a,0xee,0xd3,0xe7,0x54,0xfd,0xaa,
- 0xea,0x57,0x55,0x90,0xe1,0x18,0x4e,0xfc,0x07,0x20,0xac,0x00,0x47,0x5d,0xdd,0x02,
- 0xcf,0xad,0xff,0x6d,0xfe,0x7f,0xf3,0xdc,0x5a,0xf2,0xc0,0xd7,0x57,0xc1,0x4a,0x90,
- 0xbd,0xdf,0xbd,0xd5,0xf3,0x8d,0xef,0x3d,0x38,0x7f,0xc1,0x02,0xf8,0x3a,0xfe,0x2f,
- 0x8f,0xe7,0xd6,0x79,0x9e,0x85,0xf3,0xbc,0xe5,0xb0,0x0a,0x32,0xe6,0x97,0x56,0x2c,
- 0xf0,0x56,0x78,0x3d,0xf0,0x0d,0x10,0x4a,0x3b,0xae,0xe2,0xcf,0x33,0x8f,0x7f,0xe5,
- 0x9b,0x1e,0x60,0x02,0x00,0x4c,0xf3,0x08,0x21,0xfe,0xff,0x65,0x8f,0xa0,0x0a,0xc0,
- 0xaa,0x8a,0x3d,0x60,0xf0,0xff,0x0d,0xe3,0xbf,0xcf,0xf0,0x80,0x6a,0xfd,0xdf,0x82,
- 0x07,0x34,0x08,0x82,0xd6,0xca,0xb2,0xe1,0x2f,0xf8,0xa1,0x12,0x9b,0x18,0xfe,0x45,
- 0xf3,0x61,0x72,0xfe,0xd5,0xe3,0xec,0x3f,0x9c,0x94,0xfc,0xa9,0x3a,0xaf,0x8f,0x8f,
- 0x18,0xf1,0xfc,0xcf,0xa7,0x0b,0x01,0x98,0xb8,0xeb,0x0f,0xdf,0xfc,0x4b,0xee,0xbf,
- 0xf0,0xf3,0x89,0xfb,0xff,0xaf,0xce,0x07,0xe5,0x2f,0x98,0x8e,0xef,0x3b,0x31,0xf8,
- 0xa1,0x22,0x68,0xb0,0x1c,0xd2,0x41,0x60,0x10,0x82,0xbc,0xff,0x60,0xb0,0xb0,0x77,
- 0x62,0xfe,0xd1,0xb4,0x31,0xef,0x29,0x71,0x61,0x7e,0xd6,0xe7,0x62,0x25,0xbc,0x0a,
- 0x0b,0x8c,0xcc,0x11,0xf1,0x0a,0x8c,0x42,0x45,0x9f,0x3d,0x2e,0x8e,0xc1,0xc7,0x50,
- 0x05,0x77,0xb3,0x1c,0x0f,0xd4,0x8f,0xcf,0x37,0xf2,0x9e,0x57,0x8e,0xab,0x5e,0x95,
- 0x7e,0x4e,0x7e,0x01,0x2d,0xe0,0x8c,0xdb,0xbb,0xc9,0x47,0xd0,0xad,0x16,0xbc,0x69,
- 0xef,0xc4,0xc1,0x06,0x56,0xa2,0xd2,0x08,0x89,0x49,0x13,0xab,0xd8,0x27,0xed,0x86,
- 0x2d,0xb6,0x39,0xb0,0x61,0x01,0x91,0x60,0xab,0x50,0x62,0xe4,0x79,0xc8,0x49,0x38,
- 0x2c,0xbb,0x5e,0xa4,0x1e,0x32,0x04,0x3b,0xc1,0x0d,0x54,0x99,0xe3,0x15,0x26,0xef,
- 0x8f,0xf3,0x7f,0x02,0x4e,0x0f,0x8d,0x39,0x77,0x6b,0x3f,0x65,0x45,0xf1,0xbc,0x18,
- 0x4e,0x3b,0xbc,0x41,0x35,0x32,0x3a,0xc8,0x50,0xd8,0x46,0x4b,0x08,0xdd,0x8c,0xf7,
- 0x0f,0x8d,0xcf,0xaf,0x9e,0x3e,0x04,0xbf,0x82,0x32,0x4f,0x56,0x4c,0x74,0x85,0xdf,
- 0x3a,0xeb,0x1b,0x76,0xc7,0x6a,0x86,0x60,0x94,0x55,0xf4,0xb4,0xea,0xe2,0x71,0xe9,
- 0x8f,0xbf,0xf2,0x45,0xdd,0x11,0x41,0x91,0x26,0xee,0xaf,0x0b,0xcf,0xc1,0xc7,0xb4,
- 0x0a,0x1c,0x9e,0x1b,0xfb,0xc8,0x7b,0xb0,0xd0,0x98,0x36,0x2c,0x8e,0x09,0x97,0x33,
- 0x9e,0x37,0xb2,0x7a,0xc4,0x0f,0xe0,0xa2,0xe4,0x63,0x0e,0x2a,0x0e,0xc2,0xc4,0xfd,
- 0xfb,0x95,0xdd,0xf4,0x7d,0xcd,0x0b,0xfc,0xfe,0xd2,0x1f,0x7b,0x7c,0x41,0x7b,0xac,
- 0x60,0x08,0x2e,0x41,0x99,0x61,0x67,0xe2,0xfb,0xf0,0x47,0xcd,0x13,0xb5,0x47,0x65,
- 0x8f,0xa4,0x4e,0xbc,0x6f,0x9a,0x8f,0xb6,0xc4,0x43,0x0b,0xe4,0x61,0xb1,0x4e,0x6a,
- 0x31,0xd4,0xb7,0x6d,0x31,0x71,0x37,0xec,0x85,0x02,0x83,0x32,0x32,0xc8,0x36,0x80,
- 0x93,0xd1,0x28,0x29,0xc3,0xdd,0x3f,0xf1,0xbe,0xab,0xb5,0xf6,0x3b,0x74,0xdd,0xe6,
- 0x21,0x76,0xd8,0xa9,0xba,0xe2,0x19,0x7c,0x7d,0x76,0x42,0xa1,0xe1,0x82,0xf4,0x8d,
- 0x64,0x07,0xa8,0x1a,0x55,0xc9,0x08,0x9e,0x95,0xc4,0xcf,0x88,0xf2,0xb5,0x8c,0x8d,
- 0xb1,0xfc,0x8e,0x1b,0xbf,0x4f,0xbe,0x46,0xd7,0xeb,0x73,0x87,0xe4,0x35,0xe4,0x09,
- 0xa8,0xea,0x56,0xe3,0x74,0x0d,0x79,0x27,0xf3,0x49,0x96,0x1f,0xa2,0xdf,0x82,0x2b,
- 0x93,0xf7,0x0f,0xd0,0xa5,0xf0,0x6e,0xbb,0x1a,0xce,0xf2,0x88,0x76,0xf8,0xa3,0x5e,
- 0x39,0x96,0xe9,0x11,0x4f,0xc2,0xa7,0xd1,0x05,0x71,0x3b,0x1f,0x9c,0x85,0x98,0xe6,
- 0xae,0xa8,0x79,0x8d,0x4c,0xec,0x07,0x2d,0xad,0x55,0xfd,0x47,0xa5,0x8a,0x39,0x86,
- 0xc5,0x21,0xed,0x8a,0xb2,0xb0,0x37,0x0b,0xd7,0x07,0x3e,0x85,0xaa,0x97,0x1c,0x31,
- 0x1c,0xfc,0x7f,0x94,0xaa,0x5a,0xc7,0x48,0x8e,0x92,0x3e,0xb1,0x3e,0x54,0xfa,0x79,
- 0xb8,0x07,0x4f,0x75,0xd6,0x01,0x71,0x35,0x9c,0x80,0x32,0x96,0x19,0x13,0x87,0x70,
- 0x7e,0x59,0x9f,0x3d,0x8a,0x83,0x13,0xcc,0x1b,0xb7,0xbb,0xe4,0xa2,0xc9,0xfd,0xd3,
- 0x97,0xb7,0x5d,0x5d,0x0f,0x3b,0x80,0x7e,0x57,0x9c,0x49,0x70,0xc0,0xdc,0xf5,0xe4,
- 0x6d,0x38,0x00,0xfa,0xc9,0x40,0x30,0xfb,0x6d,0xfc,0x43,0xd5,0xa0,0x21,0x9b,0x77,
- 0xf2,0xfb,0xaa,0xb0,0x91,0xb5,0x1a,0x05,0xaa,0xad,0xdc,0xb6,0x0c,0x1e,0x63,0xea,
- 0xd9,0xeb,0xf1,0x35,0xe1,0x79,0x96,0x1f,0x2f,0x5f,0xee,0x3f,0x05,0xeb,0x71,0x80,
- 0x2f,0xae,0xc2,0xc4,0xfa,0xd7,0x49,0xad,0xb0,0x35,0xa4,0xd6,0xe3,0xee,0xca,0xc4,
- 0x8d,0xa4,0x0e,0x2f,0xe7,0xeb,0xb9,0x97,0xdf,0x36,0x37,0xdc,0xab,0xed,0x8d,0xaa,
- 0x03,0xb8,0x03,0xb3,0x27,0xf7,0xe7,0xe0,0x8c,0x41,0x38,0x65,0x94,0x36,0x67,0xe9,
- 0x05,0x7f,0x0b,0xef,0xb4,0xef,0xed,0xcc,0xd4,0xf1,0xeb,0x7f,0x0e,0x5e,0x66,0xff,
- 0x40,0xfc,0x23,0x1c,0x87,0x2e,0xe6,0xd6,0xc5,0x8a,0xc9,0xe7,0x09,0x08,0x02,0x0c,
- 0xfa,0x7d,0xd4,0x01,0x62,0x9c,0x0d,0x42,0x05,0xcd,0x62,0x62,0x1c,0x46,0x58,0x05,
- 0x38,0x98,0xf8,0x2e,0x0c,0x82,0x0f,0x1c,0x86,0xf8,0x1a,0x4c,0xdc,0x9f,0x2a,0x4f,
- 0x91,0x1e,0xf6,0x94,0x96,0x19,0x15,0x3b,0xd2,0x8f,0x41,0xf8,0x76,0x1c,0x0c,0xc0,
- 0x28,0xe9,0xd2,0xec,0x8a,0x28,0xc1,0xfb,0xe0,0xd3,0x1c,0x51,0xf1,0xe8,0xe4,0xf3,
- 0x30,0x58,0xd5,0xd3,0xdc,0xaf,0x06,0x6d,0xd1,0x9c,0x55,0xb0,0x0b,0xd4,0x3a,0x7b,
- 0x94,0x0c,0xc0,0x41,0xcd,0xa9,0x45,0xa2,0xa4,0x10,0x9a,0xa1,0x44,0x93,0xa3,0x24,
- 0x3e,0x29,0x16,0xca,0xd3,0x0a,0xd3,0x5a,0xb4,0x5f,0x04,0x68,0x34,0x7d,0x00,0x32,
- 0x94,0x6f,0x6b,0xcd,0xe6,0x7c,0x8a,0xdb,0x26,0xea,0x77,0xc3,0xcf,0x61,0x9e,0x26,
- 0xf7,0x93,0x97,0x26,0xf7,0x83,0x9a,0x2b,0x09,0x0d,0x9a,0xd3,0xd8,0x90,0x9b,0xbe,
- 0x4a,0xd8,0xa1,0xa9,0x5a,0x9e,0x42,0x7a,0xf1,0xfe,0x6a,0xd0,0xa5,0xe0,0x09,0x5d,
- 0x0b,0xc5,0x9a,0x1c,0x24,0x47,0x85,0x89,0xfd,0xb0,0x26,0x33,0x04,0x11,0x38,0x02,
- 0xb8,0xdb,0x75,0xe8,0x23,0x15,0x42,0xa6,0xf9,0xbe,0xe0,0xc5,0x2b,0xb2,0xaa,0xf0,
- 0xf7,0xdd,0x64,0x88,0xa7,0xc4,0x89,0xfd,0xb9,0x2d,0xed,0x3d,0xb8,0xac,0x3d,0xaf,
- 0x39,0xda,0x72,0x3e,0x23,0xff,0xee,0xaf,0x0a,0x66,0xe1,0xfb,0x4a,0x97,0xb5,0xac,
- 0xe0,0xbc,0xd3,0xe2,0x67,0x30,0xaa,0xf9,0x82,0x8e,0x36,0xf1,0x5c,0xfa,0xc4,0x7e,
- 0xc8,0x4b,0xbb,0xc0,0x5e,0xf1,0x2c,0xd2,0xb2,0xda,0xc4,0x42,0xd7,0x2b,0x77,0x2e,
- 0x0e,0xdc,0x83,0xf3,0x85,0xcb,0x01,0xaf,0x3f,0x2b,0xda,0xb8,0x4f,0x3d,0xa6,0x96,
- 0x6a,0xf6,0xfe,0xc6,0x97,0x26,0xf7,0x4f,0x79,0xde,0x59,0x88,0xa8,0x4e,0x81,0x36,
- 0x91,0x1d,0x42,0x04,0xda,0xa3,0x36,0x86,0xab,0xd1,0x0d,0x45,0x0a,0x6d,0x12,0xf1,
- 0x57,0xe0,0x04,0xbb,0x4e,0x4e,0x4d,0xae,0x67,0xe0,0xf6,0xb5,0xb6,0x06,0xe3,0x19,
- 0xcd,0x76,0x9d,0xbf,0x10,0x1a,0x84,0xc2,0xa0,0x4d,0x21,0xb5,0xb0,0x47,0x55,0xef,
- 0xb2,0x29,0xfe,0x01,0x68,0xc0,0x17,0xcf,0x50,0xc8,0x6b,0x93,0xf2,0x67,0x9b,0xd4,
- 0x81,0x8b,0x4c,0xb4,0x40,0x74,0x65,0x07,0xc9,0x70,0x91,0x80,0xcd,0x5c,0x4f,0x67,
- 0x91,0xa6,0xb6,0x91,0x73,0xa4,0x19,0x9c,0x9a,0x2b,0x4a,0x5e,0x9a,0xdc,0x0f,0xfa,
- 0x8c,0x55,0xd0,0x03,0x15,0x81,0xac,0x68,0xce,0x1c,0x68,0xd6,0x66,0x6a,0xfc,0x7d,
- 0xe1,0xa0,0xee,0xd5,0xee,0xda,0x7e,0xcb,0x3a,0x38,0x06,0x8c,0x7f,0xfa,0xc1,0x49,
- 0xf9,0xd3,0x27,0x74,0xc0,0xa8,0x8d,0x7f,0xf4,0x25,0x03,0x91,0x4f,0xc0,0x17,0xc2,
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+ 0xd6,0x8d,0x7e,0xb3,0x19,0x5a,0x1c,0x4f,0x01,0x57,0x6a,0xd0,0x4e,0x96,0x96,0xb0,
+ 0x25,0xdb,0x8a,0x58,0xa8,0x20,0x16,0x7a,0x66,0x50,0x18,0x2f,0x7c,0x0a,0xec,0x96,
+ 0x12,0xbb,0xce,0x8b,0x36,0x56,0x18,0xa2,0x56,0x72,0x8b,0x26,0x43,0x18,0xf0,0x8d,
+ 0x67,0x27,0xd2,0x20,0xf2,0x61,0x11,0x76,0x22,0x28,0x5e,0xe2,0x58,0x18,0x22,0x2e,
+ 0x28,0x12,0xe4,0x43,0xda,0x9b,0x8a,0x50,0x6f,0x7f,0x27,0xc3,0x88,0x85,0x1d,0xa5,
+ 0x91,0x54,0xfb,0xb7,0xae,0xd1,0x3d,0x13,0xe5,0x66,0x57,0xbb,0xe3,0xf5,0x4f,0x86,
+ 0x39,0x16,0xae,0x41,0xba,0x23,0xc2,0xc4,0x58,0xb3,0x9f,0x27,0x98,0x01,0x71,0x24,
+ 0xe9,0x2c,0x5e,0x9e,0x28,0xd6,0xf9,0x30,0x05,0x47,0x49,0x4f,0xf9,0x89,0x09,0x86,
+ 0x85,0x4b,0x0e,0x94,0xc7,0x38,0x1f,0xb6,0x09,0x74,0xb4,0xce,0x7a,0xeb,0x05,0xec,
+ 0xb7,0x31,0x91,0x0f,0xa9,0x32,0x45,0x4a,0xf6,0x26,0x5e,0x8d,0x92,0x2e,0x7b,0x97,
+ 0xd1,0x52,0x50,0xa6,0x45,0x22,0x2a,0xe0,0x91,0xc5,0xf8,0xc1,0x00,0x9e,0xb0,0x53,
+ 0xa5,0xe8,0x6c,0xf1,0x43,0x34,0x2b,0x4b,0xd1,0x14,0x39,0x2a,0x8e,0xb8,0x66,0x22,
+ 0x9a,0xc2,0xf5,0xaa,0xb7,0x87,0x7c,0x49,0x79,0x21,0xdd,0xac,0xe6,0x70,0xcf,0x53,
+ 0xfa,0x48,0x27,0xe4,0x6c,0xed,0xb2,0xd2,0x07,0x9d,0x30,0x62,0xeb,0x97,0xf9,0x91,
+ 0x11,0x9b,0x38,0xbe,0xf8,0xd9,0x06,0xa5,0xcb,0x6a,0x5f,0x68,0x0c,0xde,0xc0,0x52,
+ 0xaf,0x5d,0x84,0x4d,0x17,0xc3,0xc2,0x02,0x99,0x16,0x7c,0x58,0xf0,0xe5,0x1f,0x1a,
+ 0x09,0x29,0xc6,0x09,0xce,0x87,0xaf,0x56,0x90,0x06,0xab,0x22,0x7e,0xec,0x06,0x3e,
+ 0xf4,0xc5,0x1b,0xcd,0x87,0x14,0x5a,0x4e,0x1a,0x79,0xfc,0x5e,0x28,0xc5,0xb2,0x86,
+ 0x46,0xcf,0x41,0xf1,0x88,0x66,0x58,0xaa,0x1e,0xe6,0x47,0x2c,0x95,0x80,0x6f,0x7e,
+ 0xb0,0xa4,0x74,0x92,0x66,0x24,0x6e,0x8f,0x1a,0xe0,0x24,0xab,0x24,0x4e,0xb0,0xbd,
+ 0xcd,0x8e,0x30,0xc3,0x5f,0x22,0xd4,0xfb,0xbe,0x60,0xd6,0x30,0x05,0x1f,0x02,0x0d,
+ 0x61,0xfe,0xe1,0xf5,0xa9,0xcb,0x87,0x6a,0x52,0x98,0x41,0x7f,0xfc,0x0c,0xad,0x6a,
+ 0x61,0x7c,0x98,0xb0,0x43,0x59,0xcc,0x43,0xab,0xd2,0xdd,0x6a,0x53,0x9d,0x0f,0xeb,
+ 0xc6,0xf6,0x8d,0x87,0xd0,0x0a,0xcf,0x3f,0x24,0x6d,0x1f,0x45,0xa3,0xf2,0x7a,0x88,
+ 0xa5,0x65,0x61,0xd8,0x4b,0xa1,0xdd,0xbe,0xcf,0x4b,0xe8,0x7b,0x7b,0xe1,0x18,0x64,
+ 0x07,0x63,0x53,0x93,0x25,0x38,0xd6,0x94,0x65,0xf7,0x67,0xb9,0x89,0xc8,0x35,0xa1,
+ 0x98,0xb7,0x5e,0x14,0xd7,0xab,0x8f,0x34,0xe3,0x32,0xd9,0x55,0xd7,0xb0,0xf5,0x6a,
+ 0x30,0x65,0xcd,0x5b,0xaf,0x22,0x7e,0xbc,0x47,0x9c,0xe6,0xfd,0xe1,0xe3,0xf6,0x07,
+ 0x86,0xc9,0x7e,0xdd,0x5e,0x81,0x2b,0xe0,0x9a,0x33,0x75,0xe3,0xcb,0x3f,0x98,0x59,
+ 0x7b,0x69,0xa2,0x18,0x2e,0x22,0x3d,0xf6,0xd0,0x04,0x0d,0x6f,0x87,0x4b,0x0c,0x2c,
+ 0x8b,0xe1,0x24,0x33,0x94,0x9b,0xb3,0xbe,0xf9,0xc9,0x29,0xa5,0xc1,0xd4,0x7e,0x5c,
+ 0xdf,0xc3,0x4a,0xe9,0x4c,0xca,0x1c,0x8e,0xeb,0x37,0x9b,0x86,0xf9,0x11,0x7c,0xc8,
+ 0x2e,0x46,0xf2,0x8b,0x85,0xec,0x8a,0x70,0xc3,0xe5,0xc3,0x86,0x4b,0x85,0x94,0x14,
+ 0x2c,0xc1,0x87,0x36,0xa7,0x41,0x34,0x3e,0x2c,0x64,0x66,0x26,0x97,0x6e,0xcc,0x3f,
+ 0xd6,0xf6,0xf6,0xb6,0x68,0x3e,0xa7,0x25,0xf7,0x32,0x3e,0xcc,0x63,0xc6,0xb1,0xb8,
+ 0xe1,0xf9,0x07,0xcd,0x20,0x1a,0x5f,0xfc,0xf0,0x48,0x0c,0xb9,0x29,0x50,0x9b,0x8c,
+ 0x18,0xa4,0xc0,0x62,0x6a,0x92,0x5f,0x3b,0xd9,0x26,0x0c,0xf8,0x84,0x10,0xe8,0x40,
+ 0x15,0xba,0xa1,0x09,0xf8,0xed,0xf2,0xc2,0xf8,0xf9,0xb0,0xbb,0x21,0xff,0x8c,0x87,
+ 0x1f,0xa3,0x95,0x0b,0xe9,0xf5,0xf6,0xf8,0xaa,0x56,0xfa,0x0d,0x1a,0x75,0x3c,0xd4,
+ 0x4a,0x2f,0x5e,0xe8,0x5d,0x9f,0x18,0x0f,0x85,0xb9,0x89,0xfb,0xc6,0x43,0x0a,0x15,
+ 0xdc,0xf4,0xa7,0x70,0xf7,0x3f,0xcf,0xf8,0x10,0x5c,0xc3,0x79,0xe0,0x3b,0xd7,0x24,
+ 0x1d,0xdf,0x78,0x38,0x16,0x32,0x3e,0x5c,0x3a,0x3a,0xea,0xe7,0xc3,0xf7,0xeb,0x7c,
+ 0xb8,0xb7,0x91,0x0f,0x39,0x7d,0x31,0x3e,0xdc,0x78,0x68,0x8b,0x9f,0x0f,0xaf,0xdf,
+ 0x25,0x3e,0xe4,0x58,0xf8,0xdb,0x54,0x6d,0x61,0xe0,0x4f,0x01,0x8a,0x07,0xbb,0xde,
+ 0x65,0x58,0x38,0xf5,0xd6,0xc2,0xea,0x9a,0x6b,0xfc,0xed,0xf9,0xd9,0xff,0xb8,0x8a,
+ 0xed,0xff,0x12,0xa0,0xb8,0xb0,0xf1,0x10,0xc3,0xc2,0xab,0xd7,0x16,0x36,0xd6,0x5c,
+ 0xd3,0xd0,0xbe,0xd3,0xe5,0xc3,0x4c,0xe7,0xe6,0x5f,0xa6,0x7b,0x90,0x0f,0x33,0x2f,
+ 0x6f,0x3e,0xc7,0x09,0x33,0xc3,0x51,0xb3,0x72,0xed,0x3f,0x8c,0xdf,0x04,0x83,0xb0,
+ 0xdb,0x33,0x4c,0xc8,0xc5,0xef,0xbc,0x17,0x29,0x29,0x29,0x29,0x29,0x29,0x29,0x29,
+ 0x29,0x29,0xa9,0xff,0xbb,0x78,0xed,0xa0,0xc8,0xda,0x41,0x4a,0x4a,0x4a,0x4a,0x4a,
+ 0x4a,0x4a,0x4a,0x4a,0x4a,0xea,0xd6,0xe2,0xb5,0x43,0x54,0xd6,0x0e,0x52,0x52,0x52,
+ 0x52,0x52,0x52,0x52,0x52,0x52,0x52,0x52,0xb7,0x16,0xaf,0x1d,0x54,0x5e,0x3b,0xe0,
+ 0x5f,0x91,0xbe,0x27,0x77,0xd3,0x81,0xfe,0x97,0x76,0x07,0x74,0xb6,0xee,0x73,0xf0,
+ 0x00,0xcd,0x58,0xd0,0x70,0x13,0xda,0x5d,0x94,0xd2,0xf4,0xcc,0x31,0x7b,0x69,0xdb,
+ 0x97,0x85,0x60,0xba,0x87,0x81,0x39,0x36,0x7e,0x0a,0x03,0x4e,0x30,0xfd,0x2b,0xc6,
+ 0xcc,0x09,0x67,0xe5,0xc5,0xd7,0x5f,0x09,0xa6,0x7b,0x30,0xe7,0xcc,0xdf,0x69,0x66,
+ 0xbf,0x63,0x3a,0xc1,0xf4,0x9f,0x78,0xf8,0xe0,0x11,0xa7,0xe3,0x93,0xa7,0xb7,0x04,
+ 0xd3,0x3d,0xce,0xbf,0x18,0x7f,0x50,0xf3,0x1f,0x5f,0x73,0xdc,0x86,0x47,0x57,0x54,
+ 0x83,0x9b,0xff,0x65,0x18,0x3f,0x5b,0x20,0xa8,0xf9,0x6f,0xce,0x9e,0x9e,0x87,0x7b,
+ 0x76,0x7c,0xbe,0x29,0x98,0xee,0x71,0xfe,0xc5,0xf8,0x03,0x8b,0xff,0xb5,0x6d,0x1f,
+ 0xd3,0xa5,0xcf,0xcf,0xa8,0xb7,0x6f,0x7a,0x47,0x32,0xe7,0x06,0x30,0x7e,0x0e,0x05,
+ 0x17,0xff,0x1a,0xd9,0x00,0xab,0x63,0xf7,0x06,0x17,0xff,0x62,0xfc,0x41,0xcd,0x7f,
+ 0x22,0x6d,0x0d,0xc3,0xba,0xeb,0xd9,0xa0,0xe2,0xc7,0xac,0x39,0x2c,0x7f,0x9a,0xf3,
+ 0x4e,0x30,0xfd,0x2b,0xea,0x81,0x37,0x9d,0x0d,0x9f,0xce,0x04,0x96,0xff,0xdd,0xf1,
+ 0xdf,0xfc,0xcb,0x04,0x77,0x47,0x4a,0x66,0xe6,0x94,0x93,0x59,0x31,0x1d,0x58,0xfe,
+ 0xa9,0xcd,0xb3,0xfc,0x39,0x1f,0xd4,0xfc,0x2f,0xeb,0xff,0xf5,0x9a,0xd3,0xfb,0xe3,
+ 0xe3,0x73,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,0xd8,0xfc,0xf7,0xbf,0xf6,0x8e,0xfd,
+ 0xd0,0x8a,0x93,0xb1,0xdb,0x37,0xbd,0x23,0x99,0xb5,0x39,0x96,0x3f,0x03,0x8b,0xff,
+ 0x68,0xe7,0xa9,0x67,0xed,0xec,0x57,0x3f,0x59,0xc1,0x74,0x8f,0xf3,0x2f,0xc6,0x1f,
+ 0xd8,0xfc,0xaf,0xde,0xf1,0x05,0x18,0x6d,0x6f,0x07,0x97,0x7f,0x6a,0x2c,0x7f,0x06,
+ 0x17,0xff,0x2b,0x23,0x69,0xda,0x7f,0x32,0xf1,0x7d,0x30,0xdd,0xb3,0x1f,0x39,0xe1,
+ 0xe3,0x0f,0x66,0xfe,0x4d,0xf6,0x7c,0x1c,0xbc,0xd8,0x6a,0x82,0xcd,0x9e,0x5a,0x09,
+ 0x9b,0x40,0xff,0xf5,0xff,0x13,0xdc,0xf7,0x46,0x4c,0xa8,0x12,0xaf,0xcf,0x2b,0x7b,
+ 0x6e,0x6c,0xf7,0x37,0xea,0xe7,0xba,0x8f,0xf0,0x33,0x01,0x00,
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 3158803..958af8f 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -5,6 +5,9 @@
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -31,7 +34,6 @@
#include <pci.h>
#include <sm501.h>
-
#ifdef CONFIG_VIDEO_SM501
#define SWAP32(x) ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
@@ -66,10 +68,12 @@ static const SMI_REGS init_regs_800x600 [] =
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
@@ -100,10 +104,12 @@ static const SMI_REGS init_regs_1024x768 [] =
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
@@ -144,10 +150,12 @@ static const SMI_REGS init_regs_800x600 [] =
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x221a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
{0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
@@ -178,10 +186,12 @@ static const SMI_REGS init_regs_1024x768 [] =
{0x00040, SWAP32(0x00021807)},
{0x00044, SWAP32(0x011a0a01)},
{0x00054, SWAP32(0x00000000)},
+ /* GPIO */
+ {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
/* panel control regs... */
{0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
{0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
- {0x8000C, SWAP32(0x00000000)}, /* panel fb address */
+ {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
{0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
{0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
{0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
@@ -272,6 +282,9 @@ au_image_t au_image[] = {
int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
+/*
+ * Get version of HH405 board from GPIO's
+ */
int board_revision(void)
{
unsigned long osrh_reg;
@@ -280,10 +293,6 @@ int board_revision(void)
unsigned long value;
/*
- * Get version of HH405 board from GPIO's
- */
-
- /*
* Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
*/
osrh_reg = in32(GPIO0_OSRH);
@@ -305,15 +314,13 @@ int board_revision(void)
if (value & 0x80000000) {
/* Revision 1.0 or 1.1 detected */
- return 0x0101;
+ return 1;
} else {
if (value & 0x00400000) {
/* unused */
- return 0x0103;
+ return 3;
} else {
- /* Revision >= 2.0 detected */
- /* rev. 2.x uses four SM501 GPIOs for revision coding */
- return 0x0200;
+ return 2;
}
}
}
@@ -349,6 +356,38 @@ int board_early_init_f (void)
return 0;
}
+int cf_enable(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ int i;
+
+ volatile unsigned short *fpga_ctrl =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ volatile unsigned short *fpga_status =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+
+ if (gd->board_type >= 2) {
+ if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
+ if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
+ *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
+
+ for (i=0; i<300; i++)
+ udelay(1000);
+
+ *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
+
+ for (i=0; i<20; i++)
+ udelay(1000);
+ }
+ } else {
+ *fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
+ *fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
+ }
+ }
+
+ return 0;
+}
int misc_init_r (void)
{
@@ -433,9 +472,6 @@ int misc_init_r (void)
* Write Board revision into FPGA
*/
*fpga_ctrl |= gd->board_type & 0x0003;
- if (gd->board_type >= 0x0200) {
- *fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
- }
/*
* Setup and enable EEPROM write protection
@@ -471,7 +507,7 @@ int misc_init_r (void)
contrast0 = simple_strtol(str, NULL, 16);
if (contrast0 > 255) {
printf("ERROR: contrast0 value too high (0x%lx)!\n", contrast0);
- contrast0 = 0;
+ contrast0 = 0xffffffff;
}
}
@@ -544,9 +580,9 @@ int misc_init_r (void)
*/
*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
/*
- * Set lcd clock (small epson)
+ * Set lcd clock (small epson), enable 1-wire interface
*/
- *fpga_ctrl |= LCD_CLK_08330;
+ *fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
lcd_setup(0, 1);
lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
@@ -565,8 +601,10 @@ int misc_init_r (void)
puts("VGA: SM501 with 8 MB ");
if (strcmp(str, "ppc221") == 0) {
printf("(800*600, %dbpp)\n", BPP);
+ *lcd_backlight = 0x002d; /* max. allowed brightness */
} else if (strcmp(str, "ppc231") == 0) {
printf("(1024*768, %dbpp)\n", BPP);
+ *lcd_backlight = 0x0000;
} else {
printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
return 0;
@@ -578,6 +616,8 @@ int misc_init_r (void)
#endif /* CONFIG_VIDEO_SM501 */
}
+ cf_enable();
+
return (0);
}
@@ -590,7 +630,7 @@ int checkboard (void)
{
DECLARE_GLOBAL_DATA_PTR;
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
puts ("Board: ");
@@ -608,14 +648,7 @@ int checkboard (void)
}
gd->board_type = board_revision();
- printf(", Rev %ld.%ld)\n",
- (gd->board_type >> 8) & 0xff,
- gd->board_type & 0xff);
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
+ printf(", Rev %ld.x)\n", gd->board_type);
return 0;
}
@@ -637,28 +670,27 @@ long int initdram (int board_type)
}
-int testdram (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
-
- return (0);
-}
-
-
#ifdef CONFIG_IDE_RESET
void ide_set_reset(int on)
{
+ DECLARE_GLOBAL_DATA_PTR;
+
volatile unsigned short *fpga_mode =
(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+ volatile unsigned short *fpga_status =
+ (unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
- /*
- * Assert or deassert CompactFlash Reset Pin
- */
- if (on) { /* assert RESET */
- *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
- } else { /* release RESET */
- *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
+ (gd->board_type < 2)) {
+ /*
+ * Assert or deassert CompactFlash Reset Pin
+ */
+ if (on) { /* assert RESET */
+ cf_enable();
+ *fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+ } else { /* release RESET */
+ *fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+ }
}
}
#endif /* CONFIG_IDE_RESET */
@@ -778,8 +810,7 @@ void video_get_info_str (int line_number, char *info)
strcat(str, " (Missing bd_type!");
}
- sprintf(str2, ", Rev %ld.%ld)",
- (gd->board_type >> 8) & 0xff, gd->board_type & 0xff);
+ sprintf(str2, ", Rev %ld.x)", gd->board_type);
strcat(str, str2);
strcpy(info, str);
} else {
@@ -822,7 +853,11 @@ unsigned int board_video_get_fb (void)
devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
if (devbusfn != -1) {
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
- return (addr & 0xfffffffe);
+ addr &= 0xfffffffe;
+#ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
+ addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
+#endif
+ return addr;
}
return 0;
@@ -875,3 +910,15 @@ int board_get_height (void)
}
#endif /* CONFIG_VIDEO_SM501 */
+
+
+void reset_phy(void)
+{
+#ifdef CONFIG_LXT971_NO_SLEEP
+
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
+}
diff --git a/board/esd/pmc405/Makefile b/board/esd/pmc405/Makefile
index 1281be7..741e4aa 100644
--- a/board/esd/pmc405/Makefile
+++ b/board/esd/pmc405/Makefile
@@ -30,7 +30,7 @@ CPLD = ../common/xilinx_jtag/lenval.o \
../common/xilinx_jtag/micro.o \
../common/xilinx_jtag/ports.o
-OBJS = $(BOARD).o ../common/misc.o $(CPLD)
+OBJS = $(BOARD).o ../common/misc.o ../common/cmd_loadpci.o $(CPLD)
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 33b5f77..f9e4d43 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -1,6 +1,9 @@
/*
* (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
+ *
+ * (C) Copyright 2005
+ * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -66,16 +69,27 @@ int board_early_init_f (void)
mtebc (epcr, 0xa8400000);
/*
- * Setup GPIO pins (CS6+CS7 as GPIO)
+ * Setup GPIO pins
*/
- mtdcr(cntrl0, mfdcr(cntrl0) | 0x00300000);
- /*
- * Configure GPIO pins
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
+ CFG_FPGA_DONE | \
+ CFG_XEREADY | \
+ CFG_NONMONARCH | \
+ CFG_REV1_2) << 5));
+
+ if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
+ /* rev 1.2 boards */
+ mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
+ CFG_SELF_RST) << 5));
+ }
+
+ out32(GPIO0_OR, 0);
+ out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
+
+ /* - check if rev1_2 is low, then:
+ * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA); /* setup for output */
- out32(GPIO0_OR, 0); /* outputs -> low */
return 0;
}
@@ -83,11 +97,6 @@ int board_early_init_f (void)
/* ------------------------------------------------------------------------- */
-int misc_init_f (void)
-{
- return 0; /* dummy implementation */
-}
-
int misc_init_r (void)
{
@@ -97,16 +106,30 @@ int misc_init_r (void)
gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
gd->bd->bi_flashoffset = 0;
+ out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
return (0);
}
+ushort pmc405_pci_subsys_deviceid(void)
+{
+ ulong val;
+ val = in32(GPIO0_IR);
+ if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+ if (val & CFG_NONMONARCH) { /* monarch# signal */
+ return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+ }
+ return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
+ }
+ return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+}
/*
* Check Board Identity:
*/
-
int checkboard (void)
{
+ ulong val;
+
char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
@@ -118,12 +141,18 @@ int checkboard (void)
puts(str);
}
- putc ('\n');
+ val = in32(GPIO0_IR);
+ if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+ puts(" rev1.2 (");
+ if (val & CFG_NONMONARCH) { /* monarch# signal */
+ puts("non-");
+ }
+ puts("monarch)");
+ } else {
+ puts(" <=rev1.1");
+ }
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
+ putc ('\n');
return 0;
}
@@ -145,17 +174,19 @@ long int initdram (int board_type)
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
-/* ------------------------------------------------------------------------- */
-int testdram (void)
+/* ------------------------------------------------------------------------- */
+void reset_phy(void)
{
- /* TODO: XXX XXX XXX */
- printf ("test: 16 MB - ok\n");
+#ifdef CONFIG_LXT971_NO_SLEEP
- return (0);
+ /*
+ * Disable sleep mode in LXT971
+ */
+ lxt971_no_sleep();
+#endif
}
-/* ------------------------------------------------------------------------- */
int do_cantest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c
index 445b8fc..bc5fa7c 100644
--- a/board/esd/vom405/vom405.c
+++ b/board/esd/vom405/vom405.c
@@ -97,7 +97,7 @@ int misc_init_r (void)
int checkboard (void)
{
- unsigned char str[64];
+ char str[64];
int i = getenv_r ("serial#", str, sizeof(str));
int flashcnt;
int delay;
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
index ccd0bd1..38f579b 100644
--- a/board/pm520/flash.c
+++ b/board/pm520/flash.c
@@ -242,10 +242,11 @@ static ulong flash_get_size (FPW *addr, flash_info_t *info)
case (FPW) INTEL_ID_28F256J3A:
info->flash_id += FLASH_28F256J3A;
- info->sector_count = 256;
- info->size = 0x04000000;
- info->start[0] = CFG_FLASH_BASE;
- break; /* => 64 MB */
+ /* In U-Boot we support only 32 MB (no bank-switching) */
+ info->sector_count = 256 / 2;
+ info->size = 0x04000000 / 2;
+ info->start[0] = CFG_FLASH_BASE + 0x02000000;
+ break; /* => 32 MB */
case (FPW) INTEL_ID_28F128J3A:
info->flash_id += FLASH_28F128J3A;
diff --git a/board/xilinx/xilinx_enet/emac_adapter.c b/board/xilinx/xilinx_enet/emac_adapter.c
index 1076345..5c492eb 100644
--- a/board/xilinx/xilinx_enet/emac_adapter.c
+++ b/board/xilinx/xilinx_enet/emac_adapter.c
@@ -148,7 +148,7 @@ eth_rx(void)
RecvFrameLength = PKTSIZE;
Result = XEmac_PollRecv(&Emac, (u8 *) etherrxbuff, &RecvFrameLength);
if (Result == XST_SUCCESS) {
- NetReceive((uchar)etherrxbuff, RecvFrameLength);
+ NetReceive((uchar *)etherrxbuff, RecvFrameLength);
return (1);
} else {
return (0);
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c
index 64431ab..f6b29e9 100644
--- a/cpu/ppc4xx/405gp_pci.c
+++ b/cpu/ppc4xx/405gp_pci.c
@@ -81,6 +81,10 @@
#ifdef CONFIG_PCI
+#if defined(CONFIG_PMC405)
+ushort pmc405_pci_subsys_deviceid(void);
+#endif
+
/*#define DEBUG*/
/*-----------------------------------------------------------------------------+
@@ -96,13 +100,10 @@ void pci_405gp_init(struct pci_controller *hose)
unsigned short temp_short;
unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI};
#if defined(CONFIG_CPCI405) || defined(CONFIG_PMC405)
- unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart};
- unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1};
char *ptmla_str, *ptmms_str;
-#else
+#endif
unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA};
unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS};
-#endif
#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
diff --git a/drivers/ct69000.c b/drivers/ct69000.c
index 7bcf19f..29d82e4 100644
--- a/drivers/ct69000.c
+++ b/drivers/ct69000.c
@@ -272,6 +272,9 @@ struct ctfb_chips_properties {
static const struct ctfb_chips_properties chips[] = {
{PCI_DEVICE_ID_CT_69000, 0x200000, 1, 4, -2, 3, 257, 100, 220},
+#ifdef CONFIG_USE_CPCIDVI
+ {PCI_DEVICE_ID_CT_69030, 0x400000, 1, 4, -2, 3, 257, 100, 220},
+#endif
{PCI_DEVICE_ID_CT_65555, 0x100000, 16, 4, 0, 1, 255, 48, 220}, /* NOT TESTED */
{0, 0, 0, 0, 0, 0, 0, 0, 0} /* Terminator */
};
@@ -957,6 +960,9 @@ SetDrawingEngine (int bits_per_pixel)
*/
static struct pci_device_id supported[] = {
{PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69000},
+#ifdef CONFIG_USE_CPCIDVI
+ {PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_69030},
+#endif
{}
};
@@ -1121,7 +1127,22 @@ video_hw_init (void)
pGD->cprBase = pci_mem_base; /* Dummy */
/* set up Hardware */
+#ifdef CONFIG_USE_CPCIDVI
+ if (device_id == PCI_DEVICE_ID_CT_69030) {
+ ctWrite (CT_MSR_W_O, 0x0b);
+ ctWrite (0x3cd, 0x13);
+ ctWrite_i (CT_FP_O, 0x02, 0x00);
+ ctWrite_i (CT_FP_O, 0x05, 0x00);
+ ctWrite_i (CT_FP_O, 0x06, 0x00);
+ ctWrite (0x3c2, 0x0b);
+ ctWrite_i (CT_FP_O, 0x02, 0x10);
+ ctWrite_i (CT_FP_O, 0x01, 0x09);
+ } else {
+ ctWrite (CT_MSR_W_O, 0x01);
+ }
+#else
ctWrite (CT_MSR_W_O, 0x01);
+#endif
/* set the extended Registers */
ctLoadRegs (CT_XR_O, xreg);
diff --git a/drivers/i8042.c b/drivers/i8042.c
index e21978d..5f273a2 100644
--- a/drivers/i8042.c
+++ b/drivers/i8042.c
@@ -29,6 +29,14 @@
#ifdef CONFIG_I8042_KBD
+#ifdef CONFIG_USE_CPCIDVI
+extern u8 gt_cpcidvi_in8(u32 offset);
+extern void gt_cpcidvi_out8(u32 offset, u8 data);
+
+#define in8(a) gt_cpcidvi_in8(a)
+#define out8(a, b) gt_cpcidvi_out8(a,b)
+#endif
+
#include <i8042.h>
/* defines */
@@ -318,6 +326,13 @@ int i8042_kbd_init (void)
int keymap, try;
char *penv;
+#ifdef CONFIG_USE_CPCIDVI
+ if ((penv = getenv ("console")) != NULL) {
+ if (strncmp (penv, "serial", 7) == 0) {
+ return -1;
+ }
+ }
+#endif
/* Init keyboard device (default US layout) */
keymap = KBD_US;
if ((penv = getenv ("keymap")) != NULL)
@@ -633,7 +648,11 @@ static int kbd_reset (void)
if (kbd_input_empty() == 0)
return -1;
+#ifdef CONFIG_USE_CPCIDVI
+ out8 (I8042_COMMAND_REG, 0x60);
+#else
out8 (I8042_DATA_REG, 0x60);
+#endif
if (kbd_input_empty() == 0)
return -1;
diff --git a/fs/ext2/ext2fs.c b/fs/ext2/ext2fs.c
index c21d2d6..9cf2fb7 100644
--- a/fs/ext2/ext2fs.c
+++ b/fs/ext2/ext2fs.c
@@ -389,7 +389,7 @@ int ext2fs_read_file
int blockcnt;
int log2blocksize = LOG2_EXT2_BLOCK_SIZE (node->data);
int blocksize = 1 << (log2blocksize + DISK_SECTOR_BITS);
- unsigned int filesize = node->inode.size;
+ unsigned int filesize = __le32_to_cpu(node->inode.size);
/* Adjust len so it we can't read past the end of the file. */
if (len > filesize) {
diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h
index 756bb8c..56fd9a6 100644
--- a/include/configs/CPCI2DP.h
+++ b/include/configs/CPCI2DP.h
@@ -143,8 +143,9 @@
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
#define CFG_PCI_SUBSYS_DEVICEID 0x040b /* PCI Device ID: CPCI-2DP */
#define CFG_PCI_CLASSCODE 0x0280 /* PCI Class Code: Network/Other*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs + PB0/1 */
#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
@@ -250,14 +251,15 @@
#define CFG_INIT_RAM_ADDR 0x40000000 /* use data cache */
#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
-#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/*-----------------------------------------------------------------------
* GPIO definitions
*/
#define CFG_EEPROM_WP (0x80000000 >> 13) /* GPIO13 */
+#define CFG_SELF_RST (0x80000000 >> 14) /* GPIO14 */
#define CFG_PB_LED (0x80000000 >> 16) /* GPIO16 */
#define CFG_INTA_FAKE (0x80000000 >> 23) /* GPIO23 */
diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h
index d49020d..efc3ada 100644
--- a/include/configs/CPCI405.h
+++ b/include/configs/CPCI405.h
@@ -151,8 +151,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h
index 13dbe80..1347f2a 100644
--- a/include/configs/CPCI4052.h
+++ b/include/configs/CPCI4052.h
@@ -178,8 +178,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index aaaafa9..9d52815 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -161,8 +161,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index 5cd9aba..946a0fd 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -183,8 +183,8 @@
#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
#define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h
index 8bfd0ee..1632f37 100644
--- a/include/configs/CPCI750.h
+++ b/include/configs/CPCI750.h
@@ -70,10 +70,12 @@
#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
/*#define CFG_HUSH_PARSER*/
-#undef CFG_HUSH_PARSER
+#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
+#define CFG_AUTO_COMPLETE 1
+
/* Define which ETH port will be used for connecting the network */
#define CFG_ETH_PORT ETH_0
@@ -155,6 +157,18 @@
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
+#define CONFIG_USE_CPCIDVI
+
+#ifdef CONFIG_USE_CPCIDVI
+#define CONFIG_VIDEO
+#define CONFIG_VIDEO_CT69000
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_I8042_KBD
+#define CFG_ISA_IO 0
+#endif
+
/*
* Miscellaneous configurable options
*/
@@ -271,13 +285,19 @@
* FLASH related
*----------------------------------------------------------------------*/
+#define CFG_FLASH_CFI_DRIVER
#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
-#define CFG_FLASH_INCREMENT 0x01000000 /* there is only one bank */
#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
+#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
+#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */
+#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
+ CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \
+ CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \
+ CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
+#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
/* areas to map different things with the GT in physical space */
#define CFG_DRAM_BANKS 4
@@ -401,6 +421,8 @@
#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
#define CFG_PCI1_IO_SPACE_PCI 0x00000000
+#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
+
#if defined (CONFIG_750CX)
#define CFG_PCI_IDSEL 0x0
#else
diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index 131c215..4f62b8a 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -5,6 +5,9 @@
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
+ * (C) Copyright 2006
+ * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
+ *
* See file CREDITS for list of people who contributed to this
* project.
*
@@ -61,9 +64,13 @@
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
+#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
@@ -79,6 +86,7 @@
#else
#define CONFIG_VIDEO_SM501_16BPP
#endif
+#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VGA_AS_SINGLE_DEVICE
@@ -434,9 +442,12 @@
#define CFG_FPGA_CTRL_VGA0_BL_MODE 0x0008
#define CFG_FPGA_CTRL_CF_RESET 0x0040
#define CFG_FPGA_CTRL_PS2_PWR 0x0080
-#define CFG_FPGA_CTRL_CF_PWR 0x0100 /* low active */
+#define CFG_FPGA_CTRL_CF_PWRN 0x0100 /* low active */
#define CFG_FPGA_CTRL_CF_BUS_EN 0x0200
#define CFG_FPGA_CTRL_LCD_CLK 0x7000 /* Mask for lcd clock */
+#define CFG_FPGA_CTRL_OW_ENABLE 0x8000
+
+#define CFG_FPGA_STATUS_CF_DETECT 0x8000
#define LCD_CLK_OFF 0x0000 /* Off */
#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
diff --git a/include/configs/PM520.h b/include/configs/PM520.h
index 812bfd0..e73ad51 100644
--- a/include/configs/PM520.h
+++ b/include/configs/PM520.h
@@ -327,11 +327,11 @@
#define CFG_CS0_SIZE CFG_BOOTROM_SIZE
#define CFG_CS1_START CFG_FLASH_BASE
#define CFG_CS1_SIZE CFG_FLASH_SIZE
-#define CFG_CS1_CFG 0x0004fb00
+#define CFG_CS1_CFG 0x0004FF00
#else
#define CFG_BOOTCS_START CFG_FLASH_BASE
#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
-#define CFG_BOOTCS_CFG 0x0004fb00
+#define CFG_BOOTCS_CFG 0x0004FF00
#define CFG_CS0_START CFG_FLASH_BASE
#define CFG_CS0_SIZE CFG_FLASH_SIZE
#define CFG_CS1_START CFG_DOC_BASE
diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h
index 8bcab0b..6e0bd7f 100644
--- a/include/configs/PMC405.h
+++ b/include/configs/PMC405.h
@@ -53,9 +53,15 @@
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
+#define CONFIG_NET_MULTI 1
+#undef CONFIG_HAS_ETH1
+
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
+#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
+
+#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
CFG_CMD_BSP | \
@@ -154,15 +160,24 @@
#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CFG_PCI_SUBSYS_DEVICEID 0x0408 /* PCI Device ID: PMC-405 */
+#define CFG_PCI_SUBSYS_DEVICEID_NONMONARCH 0x0408 /* PCI Device ID: Non-Monarch */
+#define CFG_PCI_SUBSYS_DEVICEID_MONARCH 0x0409 /* PCI Device ID: Monarch */
+#define CFG_PCI_SUBSYS_DEVICEID pmc405_pci_subsys_deviceid()
+
#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
+
+#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */
+#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
+#if 1
+#define CFG_PCI_PTM2LA 0xef000000 /* point to internal regs */
+#define CFG_PCI_PTM2MS 0xff000001 /* 16MB, enable */
+#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
+#else /* old mapping */
#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
+#endif
/*-----------------------------------------------------------------------
* Start addresses for the final memory configuration
* (Set up by the startup code)
@@ -259,7 +274,7 @@
#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
#define CAN_BA 0xF0000000 /* CAN Base Address */
#define RTC_BA 0xF0000500 /* RTC Base Address */
-#define CF_BA 0xF0100000 /* CompactFlash Base Address */
+#define NVRAM_BA 0xF0200000 /* NVRAM Base Address */
/* Memory Bank 0 (Flash Bank 0) initialization */
#define CFG_EBC_PB0AP 0x92015480
@@ -273,9 +288,11 @@
#define CFG_EBC_PB2AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
-#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
+/* Memory Bank 3 -> unused */
+
+/* Memory Bank 4 (NVRAM) initialization */
+#define CFG_EBC_PB4AP 0x03000440 /* TWT=5,TH=2,CSN=0,OEN=0,WBN=0,WBF=0 */
+#define CFG_EBC_PB4CR NVRAM_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
/*-----------------------------------------------------------------------
* FPGA stuff
@@ -293,6 +310,15 @@
#define CFG_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */
/*-----------------------------------------------------------------------
+ * GPIOs
+ */
+#define CFG_NONMONARCH (0x80000000 >> 14) /* GPIO24 */
+#define CFG_XEREADY (0x80000000 >> 15) /* GPIO15 */
+#define CFG_INTA_FAKE (0x80000000 >> 19) /* GPIO19 */
+#define CFG_SELF_RST (0x80000000 >> 21) /* GPIO21 */
+#define CFG_REV1_2 (0x80000000 >> 23) /* GPIO23 */
+
+/*-----------------------------------------------------------------------
* Definitions for initial stack pointer and data area (in data cache)
*/
diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h
index c0cc4f1..773d5d2 100644
--- a/include/configs/inka4x0.h
+++ b/include/configs/inka4x0.h
@@ -101,7 +101,7 @@
/*
* Autobooting
*/
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
#define CONFIG_PREBOOT "echo;" \
"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
@@ -109,6 +109,16 @@
#undef CONFIG_BOOTARGS
+#define CONFIG_ETHADDR 00:a0:a4:03:00:00
+#define CONFIG_OVERWRITE_ETHADDR_ONCE
+
+#define CONFIG_IPADDR 192.168.100.2
+#define CONFIG_SERVERIP 192.168.100.1
+#define CONFIG_NETMASK 255.255.255.0
+#define HOSTNAME inka4x0
+#define CONFIG_BOOTFILE /tftpboot/inka4x0/uImage
+#define CONFIG_ROOTPATH /opt/eldk/ppc_6xx
+
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
@@ -117,13 +127,22 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "flash_nfs=run nfsargs addip;" \
+ "addcons=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate}\0" \
+ "flash_nfs=run nfsargs addip addcons;" \
"bootm ${kernel_addr}\0" \
- "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
- "rootpath=/opt/eldk/ppc_82xx\0" \
+ "net_nfs=tftp 200000 ${bootfile};" \
+ "run nfsargs addip addcons;bootm\0" \
+ "enable_disp=mw.l 100000 04000000 1;" \
+ "cp.l 100000 f0000b20 1;" \
+ "cp.l 100000 f0000b28 1\0" \
+ "ideargs=setenv bootargs root=/dev/hda1 rw\0" \
+ "ide_boot=ext2load ide 0:1 200000 uImage;" \
+ "run ideargs addip addcons enable_disp;bootm" \
+ "brightness=255\0" \
""
-#define CONFIG_BOOTCOMMAND "run net_nfs"
+#define CONFIG_BOOTCOMMAND "run ide_boot"
/*
* IPB Bus clocking configuration.
@@ -193,6 +212,7 @@
*/
/* #define CONFIG_FEC_10MBIT 1 */
#define CONFIG_PHY_ADDR 0x00
+#define CONFIG_MII
/*
* GPIO configuration
diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h
new file mode 100644
index 0000000..e106b3b
--- /dev/null
+++ b/include/configs/smmaco4.h
@@ -0,0 +1,373 @@
+/*
+ * (C) Copyright 2003-2006
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2004-2005
+ * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
+#define CONFIG_TQM5200 1 /* ... on TQM5200 module */
+#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */
+
+#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
+
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM 0x02 /* Software reboot */
+
+#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
+#endif
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/* Partitions */
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+#define CONFIG_ISO_PARTITION
+
+/* POST support */
+#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CPU | \
+ CFG_POST_I2C)
+
+#ifdef CONFIG_POST
+#define CFG_CMD_POST_DIAG CFG_CMD_DIAG
+/* preserve space for the post_word at end of on-chip SRAM */
+#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
+#else
+#define CFG_CMD_POST_DIAG 0
+#endif
+
+/*
+ * Supported commands
+ */
+#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
+ CFG_CMD_ASKENV | \
+ CFG_CMD_DATE | \
+ CFG_CMD_DHCP | \
+ CFG_CMD_ECHO | \
+ CFG_CMD_EEPROM | \
+ CFG_CMD_I2C | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_MII | \
+ CFG_CMD_NFS | \
+ CFG_CMD_PING | \
+ CFG_CMD_POST_DIAG | \
+ CFG_CMD_REGINFO | \
+ CFG_CMD_SNTP )
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+#define CONFIG_TIMESTAMP /* display image timestamps */
+
+#if (TEXT_BASE == 0xFC000000) /* Boot low */
+# define CFG_LOWBOOT 1
+#endif
+
+/*
+ * Autobooting
+ */
+#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "rootpath=/opt/eldk/ppc_6xx\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "flash_self=run ramargs addip;" \
+ "bootm ${kernel_addr} ${ramdisk_addr}\0" \
+ "flash_nfs=run nfsargs addip;" \
+ "bootm ${kernel_addr}\0" \
+ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
+ "bootfile=/tftpboot/smmaco4/uImage\0" \
+ "load=tftp 200000 ${u-boot}\0" \
+ "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \
+ "update=protect off FC000000 FC05FFFF;" \
+ "erase FC000000 FC05FFFF;" \
+ "cp.b 200000 FC000000 ${filesize};" \
+ "protect on FC000000 FC05FFFF\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run net_nfs"
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CFG_IPBSPEED_133 /* define for 133MHz speed */
+
+#if defined(CFG_IPBSPEED_133)
+/*
+ * PCI Bus clocking configuration
+ *
+ * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
+ * CFG_IPBSPEED_133 is defined. This is because a PCI Clock of 66 MHz yet hasn't
+ * been tested with a IPB Bus Clock of 66 MHz.
+ */
+#define CFG_PCISPEED_66 /* define for 66MHz speed */
+#endif
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
+#ifdef CONFIG_TQM5200_REV100
+#define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */
+#else
+#define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */
+#endif
+
+/*
+ * I2C clock frequency
+ *
+ * Please notice, that the resulting clock frequency could differ from the
+ * configured value. This is because the I2C clock is derived from system
+ * clock over a frequency divider with only a few divider values. U-boot
+ * calculates the best approximation for CFG_I2C_SPEED. However the calculated
+ * approximation allways lies below the configured value, never above.
+ */
+#define CFG_I2C_SPEED 100000 /* 100 kHz */
+#define CFG_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work
+ * also). For other EEPROMs configuration should be verified. On Mini-FAP the
+ * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the
+ * same configuration could be used.
+ */
+#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
+#define CFG_I2C_EEPROM_ADDR_LEN 2
+#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
+
+/*
+ * Flash configuration
+ */
+#define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */
+
+/* use CFI flash driver if no module variant is spezified */
+#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
+#define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START }
+#define CFG_FLASH_EMPTY_INFO
+#define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */
+#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */
+#undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */
+
+#if !defined(CFG_LOWBOOT)
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000)
+#else /* CFG_LOWBOOT */
+#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000)
+#endif /* CFG_LOWBOOT */
+#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks
+ (= chip selects) */
+#define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
+#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
+
+/* Dynamic MTD partition support */
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT "nor0=TQM5200-0"
+#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \
+ "1408k(kernel)," \
+ "2m(initrd)," \
+ "4m(small-fs)," \
+ "16m(big-fs)," \
+ "8m(misc)"
+
+/*
+ * Environment settings
+ */
+#define CFG_ENV_IS_IN_FLASH 1
+#define CFG_ENV_SIZE 0x10000
+#define CFG_ENV_SECT_SIZE 0x20000
+#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
+
+/*
+ * Memory map
+ */
+#define CFG_MBAR 0xF0000000
+#define CFG_SDRAM_BASE 0x00000000
+#define CFG_DEFAULT_MBAR 0x80000000
+
+/* Use ON-Chip SRAM until RAM will be available */
+#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
+#ifdef CONFIG_POST
+/* preserve space for the post_word at end of on-chip SRAM */
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
+#else
+#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE
+#endif
+
+
+#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
+
+#define CFG_MONITOR_BASE TEXT_BASE
+#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
+# define CFG_RAMBOOT 1
+#endif
+
+#define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
+#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
+#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC 1
+/*
+ * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
+ */
+/* #define CONFIG_FEC_10MBIT 1 */
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ *
+ * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1):
+ * Bit 0 (mask: 0x80000000): 1
+ * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
+ * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting.
+ * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1.
+ * Use for REV200 STK52XX boards. Do not use with REV100 modules
+ * (because, there I2C1 is used as I2C bus)
+ * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
+ * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030)
+ * 000 -> All PSC2 pins are GIOPs
+ * 001 -> CAN1/2 on PSC2 pins
+ * Use for REV100 STK52xx boards
+ * use PSC6:
+ * on STK52xx:
+ * use as UART. Pins PSC6_0 to PSC6_3 are used.
+ * Bits 9:11 (mask: 0x00700000):
+ * 101 -> PSC6 : Extended POST test is not available
+ * on MINI-FAP and TQM5200_IB:
+ * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000):
+ * 000 -> PSC6 could not be used as UART, CODEC or IrDA
+ * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST
+ * tests.
+ */
+#if defined (CONFIG_MINIFAP)
+# define CFG_GPS_PORT_CONFIG 0x91000004
+#elif defined (CONFIG_STK52XX)
+# if defined (CONFIG_STK52XX_REV100)
+# define CFG_GPS_PORT_CONFIG 0x81500014
+# else /* STK52xx REV200 and above */
+# if defined (CONFIG_TQM5200_REV100)
+# error TQM5200 REV100 not supported on STK52XX REV200 or above
+# else/* TQM5200 REV200 and above */
+# define CFG_GPS_PORT_CONFIG 0x91500004
+# endif
+# endif
+#else /* TMQ5200 Inbetriebnahme-Board */
+# define CFG_GPS_PORT_CONFIG 0x81000004
+#endif
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CFG_LONGHELP /* undef to save memory */
+#define CFG_PROMPT "=> " /* Monitor Command Prompt */
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
+#else
+#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
+#endif
+#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define CFG_MAXARGS 16 /* max number of command args */
+#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
+
+/* Enable an alternate, more extensive memory test */
+#define CFG_ALT_MEMTEST
+
+#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
+#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
+
+#define CFG_LOAD_ADDR 0x100000 /* default load address */
+
+#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
+
+/*
+ * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
+ * which is normally part of the default commands (CFV_CMD_DFL)
+ */
+#define CONFIG_LOOPW
+
+/*
+ * Various low-level settings
+ */
+#if defined(CONFIG_MPC5200)
+#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
+#define CFG_HID0_FINAL HID0_ICE
+#else
+#define CFG_HID0_INIT 0
+#define CFG_HID0_FINAL 0
+#endif
+
+#define CFG_BOOTCS_START CFG_FLASH_BASE
+#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
+#ifdef CFG_PCISPEED_66
+#define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */
+#else
+#define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */
+#endif
+#define CFG_CS0_START CFG_FLASH_BASE
+#define CFG_CS0_SIZE CFG_FLASH_SIZE
+
+#define CFG_CS_BURST 0x00000000
+#define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */
+
+#define CFG_RESET_ADDRESS 0xff000000
+
+#endif /* __CONFIG_H */
diff --git a/include/pci_ids.h b/include/pci_ids.h
index 7dec378..8cc3ec0 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -510,6 +510,7 @@
#define PCI_DEVICE_ID_CT_65554 0x00e4
#define PCI_DEVICE_ID_CT_65555 0x00e5
#define PCI_DEVICE_ID_CT_69000 0x00c0
+#define PCI_DEVICE_ID_CT_69030 0x0c30
#define PCI_VENDOR_ID_MIRO 0x1031
#define PCI_DEVICE_ID_MIRO_36050 0x5601
diff --git a/include/version.h b/include/version.h
index 4f8b498..b56d2e9 100644
--- a/include/version.h
+++ b/include/version.h
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@@ -24,6 +24,6 @@
#ifndef __VERSION_H__
#define __VERSION_H__
-#define U_BOOT_VERSION "U-Boot 1.1.4"
+#include "version_autogenerated.h"
#endif /* __VERSION_H__ */
diff --git a/lib_arm/board.c b/lib_arm/board.c
index fa3c92e..3048cbe 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2002
+ * (C) Copyright 2002-2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
@@ -25,6 +25,19 @@
* MA 02111-1307 USA
*/
+/*
+ * To match the U-Boot user interface on ARM platforms to the U-Boot
+ * standard (as on PPC platforms), some messages with debug character
+ * are removed from the default U-Boot build.
+ *
+ * Define DEBUG here if you want additional info as shown below
+ * printed upon startup:
+ *
+ * U-Boot code: 00F00000 -> 00F3C774 BSS: -> 00FC3274
+ * IRQ Stack: 00ebff7c
+ * FIQ Stack: 00ebef7c
+ */
+
#include <common.h>
#include <command.h>
#include <malloc.h>
@@ -120,14 +133,14 @@ static int init_baudrate (void)
static int display_banner (void)
{
printf ("\n\n%s\n\n", version_string);
- printf ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
- _armboot_start, _bss_start, _bss_end);
+ debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
+ _armboot_start, _bss_start, _bss_end);
#ifdef CONFIG_MODEM_SUPPORT
- puts ("Modem Support enabled\n");
+ debug ("Modem Support enabled\n");
#endif
#ifdef CONFIG_USE_IRQ
- printf ("IRQ Stack: %08lx\n", IRQ_STACK_START);
- printf ("FIQ Stack: %08lx\n", FIQ_STACK_START);
+ debug ("IRQ Stack: %08lx\n", IRQ_STACK_START);
+ debug ("FIQ Stack: %08lx\n", FIQ_STACK_START);
#endif
return (0);
@@ -145,12 +158,22 @@ static int display_dram_config (void)
DECLARE_GLOBAL_DATA_PTR;
int i;
+#ifdef DEBUG
puts ("RAM Configuration:\n");
for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
printf ("Bank #%d: %08lx ", i, gd->bd->bi_dram[i].start);
print_size (gd->bd->bi_dram[i].size, "\n");
}
+#else
+ ulong size = 0;
+
+ for (i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+ size += gd->bd->bi_dram[i].size;
+ }
+ puts("DRAM: ");
+ print_size(size, "\n");
+#endif
return (0);
}
@@ -187,6 +210,8 @@ static void display_flash_config (ulong size)
*/
typedef int (init_fnc_t) (void);
+int print_cpuinfo (void); /* test-only */
+
init_fnc_t *init_sequence[] = {
cpu_init, /* basic cpu dependent setup */
board_init, /* basic board dependent setup */
@@ -196,11 +221,14 @@ init_fnc_t *init_sequence[] = {
serial_init, /* serial communications setup */
console_init_f, /* stage 1 init of console */
display_banner, /* say that we are here */
+#if defined(CONFIG_DISPLAY_CPUINFO)
+ print_cpuinfo, /* display cpu info (and speed) */
+#endif
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+ checkboard, /* display board info */
+#endif
dram_init, /* configure available RAM banks */
display_dram_config,
-#if defined(CONFIG_VCMA9) || defined (CONFIG_CMC_PU2)
- checkboard,
-#endif
NULL,
};
@@ -301,6 +329,17 @@ void start_armboot (void)
if (s)
s = (*e) ? e + 1 : e;
}
+
+#ifdef CONFIG_HAS_ETH1
+ i = getenv_r ("eth1addr", tmp, sizeof (tmp));
+ s = (i > 0) ? tmp : NULL;
+
+ for (reg = 0; reg < 6; ++reg) {
+ gd->bd->bi_enet1addr[reg] = s ? simple_strtoul (s, &e, 16) : 0;
+ if (s)
+ s = (*e) ? e + 1 : e;
+ }
+#endif
}
devices_init (); /* get the devices list going. */
diff --git a/tools/mkimage.c b/tools/mkimage.c
index fbc1a12..70452db 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -383,7 +383,7 @@ NXTARG: ;
if (opt_type == IH_TYPE_MULTI || opt_type == IH_TYPE_SCRIPT) {
char *file = datafile;
- unsigned long size;
+ uint32_t size;
for (;;) {
char *sep = NULL;
diff --git a/tools/setlocalversion b/tools/setlocalversion
new file mode 100755
index 0000000..9a23825
--- /dev/null
+++ b/tools/setlocalversion
@@ -0,0 +1,22 @@
+#!/bin/sh
+# Print additional version information for non-release trees.
+
+usage() {
+ echo "Usage: $0 [srctree]" >&2
+ exit 1
+}
+
+cd "${1:-.}" || usage
+
+# Check for git and a git repo.
+if head=`git rev-parse --verify HEAD 2>/dev/null`; then
+ # Do we have an untagged version?
+ if [ "`git name-rev --tags HEAD`" = "HEAD undefined" ]; then
+ printf '%s%s' -g `echo "$head" | cut -c1-8`
+ fi
+
+ # Are there uncommitted changes?
+ if git diff-files | read dummy; then
+ printf '%s' -dirty
+ fi
+fi