Merge branch 'master' of git://git.denx.de/u-boot-x86

37 files changed, 1275 insertions, 89 deletions

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 29d1120..5193ee7 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -17,6 +17,9 @@ config VENDOR_CONGATEC
 config VENDOR_COREBOOT
 	bool "coreboot"
 
+config VENDOR_DFI
+	bool "dfi"
+
 config VENDOR_EFI
 	bool "efi"
 
@@ -35,6 +38,7 @@ endchoice
 source "board/advantech/Kconfig"
 source "board/congatec/Kconfig"
 source "board/coreboot/Kconfig"
+source "board/dfi/Kconfig"
 source "board/efi/Kconfig"
 source "board/emulation/Kconfig"
 source "board/google/Kconfig"
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index b1faf8c..2837709 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -9,12 +9,60 @@
 #include <common.h>
 #include <cpu.h>
 #include <dm.h>
+#include <pci.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
+#include <asm/io.h>
 #include <asm/lapic.h>
 #include <asm/msr.h>
 #include <asm/turbo.h>
 
+#define BYT_PRV_CLK			0x800
+#define BYT_PRV_CLK_EN			(1 << 0)
+#define BYT_PRV_CLK_M_VAL_SHIFT		1
+#define BYT_PRV_CLK_N_VAL_SHIFT		16
+#define BYT_PRV_CLK_UPDATE		(1 << 31)
+
+static void hsuart_clock_set(void *base)
+{
+	u32 m, n, reg;
+
+	/*
+	 * Configure the BayTrail UART clock for the internal HS UARTs
+	 * (PCI devices) to 58982400 Hz
+	 */
+	m = 0x2400;
+	n = 0x3d09;
+	reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT);
+	writel(reg, base + BYT_PRV_CLK);
+	reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE;
+	writel(reg, base + BYT_PRV_CLK);
+}
+
+/*
+ * Configure the internal clock of both SIO HS-UARTs, if they are enabled
+ * via FSP
+ */
+int arch_cpu_init_dm(void)
+{
+	struct udevice *dev;
+	void *base;
+	int ret;
+	int i;
+
+	/* Loop over the 2 HS-UARTs */
+	for (i = 0; i < 2; i++) {
+		ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev);
+		if (!ret) {
+			base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
+					      PCI_REGION_MEM);
+			hsuart_clock_set(base);
+		}
+	}
+
+	return 0;
+}
+
 static void set_max_freq(void)
 {
 	msr_t perf_ctl;
diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile
index 4f07f41..3f534ad 100644
--- a/arch/x86/dts/Makefile
+++ b/arch/x86/dts/Makefile
@@ -9,11 +9,13 @@ dtb-y += bayleybay.dtb \
 	conga-qeval20-qa3-e3845.dtb \
 	cougarcanyon2.dtb \
 	crownbay.dtb \
+	dfi-bt700-q7x-151.dtb \
 	efi.dtb \
 	galileo.dtb \
 	minnowmax.dtb \
 	qemu-x86_i440fx.dtb \
 	qemu-x86_q35.dtb \
+	theadorable-x86-dfi-bt700.dtb \
 	broadwell_som-6896.dtb \
 	baytrail_som-db5800-som-6867.dtb
 
diff --git a/arch/x86/dts/baytrail_som-db5800-som-6867.dts b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
index 64e2e52..e1d81a7 100644
--- a/arch/x86/dts/baytrail_som-db5800-som-6867.dts
+++ b/arch/x86/dts/baytrail_som-db5800-som-6867.dts
@@ -63,6 +63,12 @@
 			pad-offset = <0x270>;
 			mode-func = <2>;
 		};
+
+		/* SERIRQ */
+		soc_gpio_s0_50@0 {
+			pad-offset = <0x560>;
+			mode-func = <1>;
+		};
 	};
 
 	chosen {
diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
index fba089d..f0efe90 100644
--- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts
+++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts
@@ -46,6 +46,17 @@
 			pad-offset = <0x3a0>;
 			mode-func = <1>;
 		};
+
+		/* Add SMBus PAD configuration */
+		smbus_clk@0 {
+			pad-offset = <0x580>;
+			mode-func = <1>;
+		};
+
+		smbus_data@0 {
+			pad-offset = <0x5a0>;
+			mode-func = <1>;
+		};
 	};
 
 	chosen {
@@ -244,13 +255,6 @@
 		fsp,lpss-sio-enable-pci-mode;
 		fsp,enable-dma0;
 		fsp,enable-dma1;
-		fsp,enable-i2c0;
-		fsp,enable-i2c1;
-		fsp,enable-i2c2;
-		fsp,enable-i2c3;
-		fsp,enable-i2c4;
-		fsp,enable-i2c5;
-		fsp,enable-i2c6;
 		fsp,enable-pwm0;
 		fsp,enable-pwm1;
 		fsp,igd-dvmt50-pre-alloc = <2>;
diff --git a/arch/x86/dts/dfi-bt700-q7x-151.dts b/arch/x86/dts/dfi-bt700-q7x-151.dts
new file mode 100644
index 0000000..31d9679
--- /dev/null
+++ b/arch/x86/dts/dfi-bt700-q7x-151.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "dfi-bt700.dtsi"
+
+#include "serial.dtsi"
+
+/ {
+	model = "DFI-BT700";
+	compatible = "dfi,bt700", "intel,baytrail";
+
+	aliases {
+		serial0 = &serial;
+		spi0 = &spi;
+	};
+};
diff --git a/arch/x86/dts/dfi-bt700.dtsi b/arch/x86/dts/dfi-bt700.dtsi
new file mode 100644
index 0000000..75ee6ad
--- /dev/null
+++ b/arch/x86/dts/dfi-bt700.dtsi
@@ -0,0 +1,308 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/gpio/x86-gpio.h>
+#include <dt-bindings/interrupt-router/intel-irq.h>
+
+#include "skeleton.dtsi"
+#include "rtc.dtsi"
+#include "tsc_timer.dtsi"
+
+/ {
+	config {
+		silent_console = <0>;
+	};
+
+	pch_pinctrl {
+		compatible = "intel,x86-pinctrl";
+		reg = <0 0>;
+
+		/* Add UART1 PAD configuration (SIO HS-UART) */
+		uart1_txd@0 {
+			pad-offset = <0x10>;
+			mode-func = <1>;
+		};
+
+		uart1_rxd@0 {
+			pad-offset = <0x20>;
+			mode-func = <1>;
+		};
+
+		/*
+		 * As of today, the latest version FSP (gold4) for BayTrail
+		 * misses the PAD configuration of the SD controller's Card
+		 * Detect signal. The default PAD value for the CD pin sets
+		 * the pin to work in GPIO mode, which causes card detect
+		 * status cannot be reflected by the Present State register
+		 * in the SD controller (bit 16 & bit 18 are always zero).
+		 *
+		 * Configure this pin to function 1 (SD controller).
+		 */
+		sdmmc3_cd@0 {
+			pad-offset = <0x3a0>;
+			mode-func = <1>;
+		};
+	};
+
+	chosen {
+		stdout-path = "/serial";
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <0>;
+			intel,apic-id = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <1>;
+			intel,apic-id = <2>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <2>;
+			intel,apic-id = <4>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,baytrail-cpu";
+			reg = <3>;
+			intel,apic-id = <6>;
+		};
+	};
+
+	pci {
+		compatible = "intel,pci-baytrail", "pci-x86";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		u-boot,dm-pre-reloc;
+		ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
+			  0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
+			  0x01000000 0x0 0x2000 0x2000 0 0xe000>;
+
+		pciuart0: uart@1e,3 {
+			compatible = "pci8086,0f0a.00",
+					"pci8086,0f0a",
+					"pciclass,070002",
+					"pciclass,0700",
+					"ns16550";
+			u-boot,dm-pre-reloc;
+			reg = <0x0200f310 0x0 0x0 0x0 0x0>;
+			reg-shift = <2>;
+			clock-frequency = <58982400>;
+			current-speed = <115200>;
+		};
+
+		pch@1f,0 {
+			reg = <0x0000f800 0 0 0 0>;
+			compatible = "pci8086,0f1c", "intel,pch9";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			irq-router {
+				compatible = "intel,irq-router";
+				intel,pirq-config = "ibase";
+				intel,ibase-offset = <0x50>;
+				intel,actl-addr = <0>;
+				intel,pirq-link = <8 8>;
+				intel,pirq-mask = <0xdee0>;
+				intel,pirq-routing = <
+					/* BayTrail PCI devices */
+					PCI_BDF(0, 2, 0) INTA PIRQA
+					PCI_BDF(0, 3, 0) INTA PIRQA
+					PCI_BDF(0, 16, 0) INTA PIRQA
+					PCI_BDF(0, 17, 0) INTA PIRQA
+					PCI_BDF(0, 18, 0) INTA PIRQA
+					PCI_BDF(0, 19, 0) INTA PIRQA
+					PCI_BDF(0, 20, 0) INTA PIRQA
+					PCI_BDF(0, 21, 0) INTA PIRQA
+					PCI_BDF(0, 22, 0) INTA PIRQA
+					PCI_BDF(0, 23, 0) INTA PIRQA
+					PCI_BDF(0, 24, 0) INTA PIRQA
+					PCI_BDF(0, 24, 1) INTC PIRQC
+					PCI_BDF(0, 24, 2) INTD PIRQD
+					PCI_BDF(0, 24, 3) INTB PIRQB
+					PCI_BDF(0, 24, 4) INTA PIRQA
+					PCI_BDF(0, 24, 5) INTC PIRQC
+					PCI_BDF(0, 24, 6) INTD PIRQD
+					PCI_BDF(0, 24, 7) INTB PIRQB
+					PCI_BDF(0, 26, 0) INTA PIRQA
+					PCI_BDF(0, 27, 0) INTA PIRQA
+					PCI_BDF(0, 28, 0) INTA PIRQA
+					PCI_BDF(0, 28, 1) INTB PIRQB
+					PCI_BDF(0, 28, 2) INTC PIRQC
+					PCI_BDF(0, 28, 3) INTD PIRQD
+					PCI_BDF(0, 29, 0) INTA PIRQA
+					PCI_BDF(0, 30, 0) INTA PIRQA
+					PCI_BDF(0, 30, 1) INTD PIRQD
+					PCI_BDF(0, 30, 2) INTB PIRQB
+					PCI_BDF(0, 30, 3) INTC PIRQC
+					PCI_BDF(0, 30, 4) INTD PIRQD
+					PCI_BDF(0, 30, 5) INTB PIRQB
+					PCI_BDF(0, 31, 3) INTB PIRQB
+
+					/*
+					 * PCIe root ports downstream
+					 * interrupts
+					 */
+					PCI_BDF(1, 0, 0) INTA PIRQA
+					PCI_BDF(1, 0, 0) INTB PIRQB
+					PCI_BDF(1, 0, 0) INTC PIRQC
+					PCI_BDF(1, 0, 0) INTD PIRQD
+					PCI_BDF(2, 0, 0) INTA PIRQB
+					PCI_BDF(2, 0, 0) INTB PIRQC
+					PCI_BDF(2, 0, 0) INTC PIRQD
+					PCI_BDF(2, 0, 0) INTD PIRQA
+					PCI_BDF(3, 0, 0) INTA PIRQC
+					PCI_BDF(3, 0, 0) INTB PIRQD
+					PCI_BDF(3, 0, 0) INTC PIRQA
+					PCI_BDF(3, 0, 0) INTD PIRQB
+					PCI_BDF(4, 0, 0) INTA PIRQD
+					PCI_BDF(4, 0, 0) INTB PIRQA
+					PCI_BDF(4, 0, 0) INTC PIRQB
+					PCI_BDF(4, 0, 0) INTD PIRQC
+				>;
+			};
+
+			spi: spi {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "intel,ich9-spi";
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					reg = <0>;
+					compatible = "stmicro,n25q064a",
+						"spi-flash";
+					memory-map = <0xff800000 0x00800000>;
+					rw-mrc-cache {
+						label = "rw-mrc-cache";
+						reg = <0x006f0000 0x00010000>;
+					};
+				};
+			};
+
+			gpioa {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0 0x20>;
+				bank-name = "A";
+			};
+
+			gpiob {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x20 0x20>;
+				bank-name = "B";
+			};
+
+			gpioc {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x40 0x20>;
+				bank-name = "C";
+			};
+
+			gpiod {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x60 0x20>;
+				bank-name = "D";
+			};
+
+			gpioe {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0x80 0x20>;
+				bank-name = "E";
+			};
+
+			gpiof {
+				compatible = "intel,ich6-gpio";
+				u-boot,dm-pre-reloc;
+				reg = <0xA0 0x20>;
+				bank-name = "F";
+			};
+		};
+	};
+
+	fsp {
+		compatible = "intel,baytrail-fsp";
+		fsp,mrc-init-tseg-size = <0>;
+		fsp,mrc-init-mmio-size = <0x800>;
+		fsp,mrc-init-spd-addr1 = <0xa0>;
+		fsp,mrc-init-spd-addr2 = <0xa2>;
+		fsp,emmc-boot-mode = <1>;
+		fsp,enable-sdio;
+		fsp,enable-sdcard;
+		fsp,enable-hsuart0;
+		fsp,enable-hsuart1;
+		fsp,enable-spi;
+		fsp,enable-sata;
+		fsp,sata-mode = <1>;
+		fsp,enable-lpe;
+		fsp,lpss-sio-enable-pci-mode;
+		fsp,enable-dma0;
+		fsp,enable-dma1;
+		fsp,enable-i2c0;
+		fsp,enable-i2c1;
+		fsp,enable-i2c2;
+		fsp,enable-i2c3;
+		fsp,enable-i2c4;
+		fsp,enable-i2c5;
+		fsp,enable-i2c6;
+		fsp,enable-pwm0;
+		fsp,enable-pwm1;
+		fsp,igd-dvmt50-pre-alloc = <2>;
+		fsp,aperture-size = <2>;
+		fsp,gtt-size = <2>;
+		fsp,scc-enable-pci-mode;
+		fsp,os-selection = <4>;
+		fsp,emmc45-ddr50-enabled;
+		fsp,emmc45-retune-timer-value = <8>;
+		fsp,enable-igd;
+		fsp,enable-memory-down;
+		fsp,memory-down-params {
+			compatible = "intel,baytrail-fsp-mdp";
+			fsp,dram-speed = <2>;		/* 2=1333MHz */
+			fsp,dram-type = <1>;		/* 1=DDR3L */
+			fsp,dimm-0-enable;
+			fsp,dimm-width = <1>;		/* 1=x16, 2=x32 */
+			fsp,dimm-density = <3>;		/* 3=8Gbit */
+			fsp,dimm-bus-width = <3>;	/* 3=64bits */
+			fsp,dimm-sides = <0>;		/* 0=1 ranks -> 0x2b */
+
+			/* These following values might need a re-visit */
+			fsp,dimm-tcl = <8>;
+			fsp,dimm-trpt-rcd = <8>;
+			fsp,dimm-twr = <8>;
+			fsp,dimm-twtr = <4>;
+			fsp,dimm-trrd = <6>;
+			fsp,dimm-trtp = <4>;
+			fsp,dimm-tfaw = <22>;
+		};
+	};
+
+	microcode {
+		update@0 {
+#include "microcode/m0130673325.dtsi"
+		};
+		update@1 {
+#include "microcode/m0130679907.dtsi"
+		};
+	};
+};
diff --git a/arch/x86/dts/theadorable-x86-dfi-bt700.dts b/arch/x86/dts/theadorable-x86-dfi-bt700.dts
new file mode 100644
index 0000000..75f9ffa
--- /dev/null
+++ b/arch/x86/dts/theadorable-x86-dfi-bt700.dts
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+
+#include "dfi-bt700.dtsi"
+
+/ {
+	model = "theadorable-x86-DFI-BT700";
+	compatible = "anonymous,theadorable-x86-dfi-bt700", "dfi,bt700",
+			"intel,baytrail";
+
+	aliases {
+		serial0 = &pciuart0;
+		spi0 = &spi;
+	};
+};
diff --git a/arch/x86/include/asm/arch-ivybridge/pch.h b/arch/x86/include/asm/arch-ivybridge/pch.h
index 4725250..9c51f63 100644
--- a/arch/x86/include/asm/arch-ivybridge/pch.h
+++ b/arch/x86/include/asm/arch-ivybridge/pch.h
@@ -134,32 +134,6 @@
 #define SATA_IOBP_SP0G3IR	0xea000151
 #define SATA_IOBP_SP1G3IR	0xea000051
 
-/* PCI Configuration Space (D31:F3): SMBus */
-#define PCH_SMBUS_DEV		PCI_BDF(0, 0x1f, 3)
-#define SMB_BASE		0x20
-#define HOSTC			0x40
-#define SMB_RCV_SLVA		0x09
-
-/* HOSTC bits */
-#define I2C_EN			(1 << 2)
-#define SMB_SMI_EN		(1 << 1)
-#define HST_EN			(1 << 0)
-
-/* SMBus I/O bits. */
-#define SMBHSTSTAT		0x0
-#define SMBHSTCTL		0x2
-#define SMBHSTCMD		0x3
-#define SMBXMITADD		0x4
-#define SMBHSTDAT0		0x5
-#define SMBHSTDAT1		0x6
-#define SMBBLKDAT		0x7
-#define SMBTRNSADD		0x9
-#define SMBSLVDATA		0xa
-#define SMLINK_PIN_CTL		0xe
-#define SMBUS_PIN_CTL		0xf
-
-#define SMBUS_TIMEOUT		(10 * 1000 * 100)
-
 #define VCH		0x0000	/* 32bit */
 #define VCAP1		0x0004	/* 32bit */
 #define VCAP2		0x0008	/* 32bit */
diff --git a/arch/x86/include/asm/cache.h b/arch/x86/include/asm/cache.h
index 508b63f..4ff63c3 100644
--- a/arch/x86/include/asm/cache.h
+++ b/arch/x86/include/asm/cache.h
@@ -11,12 +11,12 @@
  * If CONFIG_SYS_CACHELINE_SIZE is defined use it for DMA alignment.  Otherwise
  * use 64-bytes, a safe default for x86.
  */
-#ifdef CONFIG_SYS_CACHELINE_SIZE
-#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
-#else
-#define ARCH_DMA_MINALIGN	64
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+#define CONFIG_SYS_CACHELINE_SIZE	64
 #endif
 
+#define ARCH_DMA_MINALIGN		CONFIG_SYS_CACHELINE_SIZE
+
 static inline void wbinvd(void)
 {
 	asm volatile ("wbinvd" : : : "memory");
diff --git a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
index 5a4d4dc..3d7e8e2 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
+++ b/board/congatec/conga-qeval20-qa3-e3845/MAINTAINERS
@@ -4,4 +4,5 @@ S:	Maintained
 F:	board/congatec/conga-qeval20-qa3-e3845
 F:	include/configs/conga-qeval20-qa3-e3845.h
 F:	configs/conga-qeval20-qa3-e3845_defconfig
+F:	configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
 F:	arch/x86/dts/conga-qeval20-qa3-e3845.dts
diff --git a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
index 737e610..7a5b765 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
+++ b/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <i2c.h>
 #include <winbond_w83627.h>
 #include <asm/gpio.h>
 #include <asm/ibmpc.h>
@@ -31,3 +32,42 @@ int arch_early_init_r(void)
 {
 	return 0;
 }
+
+int board_late_init(void)
+{
+	struct udevice *dev;
+	u8 buf[8];
+	int ret;
+
+	/* Configure SMSC USB2513 USB Hub: 7bit address 0x2c */
+	ret = i2c_get_chip_for_busnum(0, 0x2c, 1, &dev);
+	if (ret) {
+		printf("Cannot find USB2513: %d\n", ret);
+		return 0;
+	}
+
+	/*
+	 * The first access to the USB Hub fails sometimes, so lets read
+	 * a dummy byte to be sure here
+	 */
+	dm_i2c_read(dev, 0x00, buf, 1);
+
+	/*
+	 * The SMSC hub is not visible on the I2C bus after the first
+	 * configuration at power-up. The following code deliberately
+	 * does not report upon failure of these I2C write calls.
+	 */
+	buf[0] = 0x93;
+	dm_i2c_write(dev, 0x06, buf, 1);
+
+	buf[0] = 0xaa;
+	dm_i2c_write(dev, 0xf8, buf, 1);
+
+	buf[0] = 0x0f;
+	dm_i2c_write(dev, 0xfa, buf, 1);
+
+	buf[0] = 0x01;
+	dm_i2c_write(dev, 0xff, buf, 1);
+
+	return 0;
+}
diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig
new file mode 100644
index 0000000..25d0a11
--- /dev/null
+++ b/board/dfi/Kconfig
@@ -0,0 +1,29 @@
+#
+# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+if VENDOR_DFI
+
+choice
+	prompt "Mainboard model"
+	optional
+
+config TARGET_DFI_BT700
+	bool "DFI BT700 BayTrail"
+	help
+	  This is the DFI Q7X-151 baseboard equipped with the
+	  DFI BayTrail Bt700 SoM. It contains an Atom E3845 with
+	  Ethernet (in non-PCIe-x4 configuration), micro-SD, USB 2,
+	  USB 3, SATA, serial console and DisplayPort video out.
+	  It requires some binary blobs - see README.x86 for details.
+
+	  Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+	  by U-Boot matches that value.
+
+endchoice
+
+source "board/dfi/dfi-bt700/Kconfig"
+
+endif
diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig
new file mode 100644
index 0000000..3f0acb3
--- /dev/null
+++ b/board/dfi/dfi-bt700/Kconfig
@@ -0,0 +1,28 @@
+if TARGET_DFI_BT700
+
+config SYS_BOARD
+	default "dfi-bt700"
+
+config SYS_VENDOR
+	default "dfi"
+
+config SYS_SOC
+	default "baytrail"
+
+config SYS_CONFIG_NAME
+	default "dfi-bt700"
+
+config SYS_TEXT_BASE
+	default 0xfff00000 if !EFI_STUB
+	default 0x01110000 if EFI_STUB
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select X86_RESET_VECTOR if !EFI_STUB
+	select INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+
+config PCIE_ECAM_BASE
+	default 0xe0000000
+
+endif
diff --git a/board/dfi/dfi-bt700/MAINTAINERS b/board/dfi/dfi-bt700/MAINTAINERS
new file mode 100644
index 0000000..6639787
--- /dev/null
+++ b/board/dfi/dfi-bt700/MAINTAINERS
@@ -0,0 +1,10 @@
+congatec DFI-BT700
+M:	Stefan Roese <sr@denx.de>
+S:	Maintained
+F:	board/dfi/dfi-bt700
+F:	include/configs/dfi-bt700.h
+F:	configs/dfi-bt700-q7x-151_defconfig
+F:	configs/theadorable-x86-dfi-bt700_defconfig
+F:	arch/x86/dts/dfi-bt700.dtsi
+F:	arch/x86/dts/dfi-bt700-q7x-151.dts
+F:	arch/x86/dts/theadorable-x86-dfi-bt700.dts
diff --git a/board/dfi/dfi-bt700/Makefile b/board/dfi/dfi-bt700/Makefile
new file mode 100644
index 0000000..8052f5e
--- /dev/null
+++ b/board/dfi/dfi-bt700/Makefile
@@ -0,0 +1,8 @@
+#
+# Copyright (C) 2015, Google, Inc
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= dfi-bt700.o start.o
+obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o
diff --git a/board/dfi/dfi-bt700/acpi/mainboard.asl b/board/dfi/dfi-bt700/acpi/mainboard.asl
new file mode 100644
index 0000000..544a049
--- /dev/null
+++ b/board/dfi/dfi-bt700/acpi/mainboard.asl
@@ -0,0 +1,13 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/* Power Button */
+Device (PWRB)
+{
+	Name(_HID, EISAID("PNP0C0C"))
+}
+
+/* TODO: Need add Nuvoton SuperIO chipset NCT6102D ASL codes */
diff --git a/board/dfi/dfi-bt700/dfi-bt700.c b/board/dfi/dfi-bt700/dfi-bt700.c
new file mode 100644
index 0000000..8645bdc
--- /dev/null
+++ b/board/dfi/dfi-bt700/dfi-bt700.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nuvoton_nct6102d.h>
+#include <asm/gpio.h>
+#include <asm/ibmpc.h>
+#include <asm/pnp_def.h>
+
+int board_early_init_f(void)
+{
+#ifdef CONFIG_INTERNAL_UART
+	/* Disable the legacy UART which is enabled per default */
+	nct6102d_uarta_disable();
+#else
+	/*
+	 * The FSP enables the BayTrail internal legacy UART (again).
+	 * Disable it again, so that the Nuvoton one can be used.
+	 */
+	setup_internal_uart(0);
+#endif
+
+	/* Disable the watchdog which is enabled per default */
+	nct6102d_wdt_disable();
+
+	return 0;
+}
diff --git a/board/dfi/dfi-bt700/dsdt.asl b/board/dfi/dfi-bt700/dsdt.asl
new file mode 100644
index 0000000..6042011
--- /dev/null
+++ b/board/dfi/dfi-bt700/dsdt.asl
@@ -0,0 +1,14 @@
+/*
+ * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000)
+{
+	/* platform specific */
+	#include <asm/arch/acpi/platform.asl>
+
+	/* board specific */
+	#include "acpi/mainboard.asl"
+}
diff --git a/board/dfi/dfi-bt700/start.S b/board/dfi/dfi-bt700/start.S
new file mode 100644
index 0000000..2c941a4
--- /dev/null
+++ b/board/dfi/dfi-bt700/start.S
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2015, Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl early_board_init
+early_board_init:
+	jmp	early_board_init_ret
diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl
index 21785ea..8b7ee3f 100644
--- a/board/intel/bayleybay/acpi/mainboard.asl
+++ b/board/intel/bayleybay/acpi/mainboard.asl
@@ -9,3 +9,41 @@ Device (PWRB)
 {
 	Name(_HID, EISAID("PNP0C0C"))
 }
+
+/* PS/2 keyboard and mouse */
+Scope (\_SB.PCI0.LPCB)
+{
+	/* 8042 Keyboard */
+	Device (PS2K)
+	{
+		Name(_HID, EISAID("PNP0303"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x60, 0x60, 0x00, 0x01)
+			IO(Decode16, 0x64, 0x64, 0x00, 0x01)
+			IRQNoFlags() { 1 }
+		})
+
+		Method(_STA, 0, Serialized)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+
+	/* 8042 Mouse */
+	Device (PS2M)
+	{
+		Name(_HID, EISAID("PNP0F03"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO(Decode16, 0x60, 0x60, 0x00, 0x01)
+			IO(Decode16, 0x64, 0x64, 0x00, 0x01)
+			IRQNoFlags() { 12 }
+		})
+
+		Method(_STA, 0, Serialized)
+		{
+			Return (STA_VISIBLE)
+		}
+	}
+}
diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c
index e0bd15d..ae3027a 100644
--- a/cmd/bdinfo.c
+++ b/cmd/bdinfo.c
@@ -98,9 +98,11 @@ static inline void print_bi_dram(const bd_t *bd)
 	int i;
 
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) {
-		print_num("DRAM bank",	i);
-		print_num("-> start",	bd->bi_dram[i].start);
-		print_num("-> size",	bd->bi_dram[i].size);
+		if (bd->bi_dram[i].size) {
+			print_num("DRAM bank",	i);
+			print_num("-> start",	bd->bi_dram[i].start);
+			print_num("-> size",	bd->bi_dram[i].size);
+		}
 	}
 #endif
 }
@@ -444,16 +446,6 @@ int do_bdinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	bd_t *bd = gd->bd;
 
 	print_bi_boot_params(bd);
-	print_num("bi_memstart",	bd->bi_memstart);
-	print_num("bi_memsize",		bd->bi_memsize);
-	print_num("bi_flashstart",	bd->bi_flashstart);
-	print_num("bi_flashsize",	bd->bi_flashsize);
-	print_num("bi_flashoffset",	bd->bi_flashoffset);
-	print_num("bi_sramstart",	bd->bi_sramstart);
-	print_num("bi_sramsize",	bd->bi_sramsize);
-	print_num("bi_bootflags",	bd->bi_bootflags);
-	print_mhz("cpufreq",		bd->bi_intfreq);
-	print_mhz("busfreq",		bd->bi_busfreq);
 
 	print_bi_dram(bd);
 
diff --git a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
index 26f83ba..c0f5199 100644
--- a/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
+++ b/configs/conga-qeval20-qa3-e3845-internal-uart_defconfig
@@ -1,4 +1,5 @@
 CONFIG_X86=y
+CONFIG_DM_I2C=y
 CONFIG_VENDOR_CONGATEC=y
 CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
 CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
@@ -22,6 +23,7 @@ CONFIG_CMD_CPU=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
@@ -39,6 +41,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
+CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig
index 64fd7c9..4636322 100644
--- a/configs/conga-qeval20-qa3-e3845_defconfig
+++ b/configs/conga-qeval20-qa3-e3845_defconfig
@@ -1,4 +1,5 @@
 CONFIG_X86=y
+CONFIG_DM_I2C=y
 CONFIG_VENDOR_CONGATEC=y
 CONFIG_TARGET_CONGA_QEVAL20_QA3_E3845=y
 CONFIG_DEFAULT_DEVICE_TREE="conga-qeval20-qa3-e3845"
@@ -21,6 +22,7 @@ CONFIG_CMD_CPU=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_SF=y
 CONFIG_CMD_SPI=y
+CONFIG_CMD_I2C=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_GPIO=y
 # CONFIG_CMD_SETEXPR is not set
@@ -38,6 +40,7 @@ CONFIG_OF_CONTROL=y
 CONFIG_REGMAP=y
 CONFIG_SYSCON=y
 CONFIG_CPU=y
+CONFIG_SYS_I2C_INTEL=y
 CONFIG_WINBOND_W83627=y
 CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
diff --git a/configs/dfi-bt700-q7x-151_defconfig b/configs/dfi-bt700-q7x-151_defconfig
new file mode 100644
index 0000000..6f00004
--- /dev/null
+++ b/configs/dfi-bt700-q7x-151_defconfig
@@ -0,0 +1,63 @@
+CONFIG_X86=y
+CONFIG_DM_I2C=y
+CONFIG_VENDOR_DFI=y
+CONFIG_DEFAULT_DEVICE_TREE="dfi-bt700-q7x-151"
+CONFIG_TARGET_DFI_BT700=y
+CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_NUVOTON_NCT6102D=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_DEBUG_UART=y
+CONFIG_DEBUG_UART_BASE=0x3f8
+CONFIG_DEBUG_UART_CLOCK=1843200
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/configs/theadorable-x86-dfi-bt700_defconfig b/configs/theadorable-x86-dfi-bt700_defconfig
new file mode 100644
index 0000000..3aba157
--- /dev/null
+++ b/configs/theadorable-x86-dfi-bt700_defconfig
@@ -0,0 +1,60 @@
+CONFIG_X86=y
+CONFIG_DM_I2C=y
+CONFIG_VENDOR_DFI=y
+CONFIG_DEFAULT_DEVICE_TREE="theadorable-x86-dfi-bt700"
+CONFIG_TARGET_DFI_BT700=y
+CONFIG_HAVE_INTEL_ME=y
+CONFIG_ENABLE_MRC_CACHE=y
+CONFIG_SMP=y
+CONFIG_HAVE_VGA_BIOS=y
+CONFIG_GENERATE_PIRQ_TABLE=y
+CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_ACPI_TABLE=y
+CONFIG_SEABIOS=y
+CONFIG_FIT=y
+CONFIG_FIT_SIGNATURE=y
+CONFIG_BOOTSTAGE=y
+CONFIG_BOOTSTAGE_REPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_CPU=y
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_PING=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_BOOTSTAGE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_OF_CONTROL=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CPU=y
+CONFIG_NUVOTON_NCT6102D=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_E1000=y
+CONFIG_DM_PCI=y
+CONFIG_DM_RTC=y
+CONFIG_SYS_NS16550=y
+CONFIG_ICH_SPI=y
+CONFIG_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_VIDEO_VESA=y
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE_114=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/doc/README.x86 b/doc/README.x86
index 7d694b1..ba5bb99 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -314,6 +314,10 @@ Offset   Description         Controlling config
 
 Overall ROM image size is controlled by CONFIG_ROM_SIZE.
 
+Note that the debug version of the FSP is bigger in size. If this version
+is used, CONFIG_FSP_ADDR needs to be configured to 0xfffb0000 instead of
+the default value 0xfffc0000.
+
 ---
 
 Intel Galileo instructions for bare mode:
@@ -1035,10 +1039,39 @@ command from the OS.
 For other platform boards, ACPI support status can be checked by examining their
 board defconfig files to see if CONFIG_GENERATE_ACPI_TABLE is set to y.
 
+EFI Support
+-----------
+U-Boot supports booting as a 32-bit or 64-bit EFI payload, e.g. with UEFI.
+This is enabled with CONFIG_EFI_STUB. U-Boot can also run as an EFI
+application, with CONFIG_EFI_APP. The CONFIG_EFI_LOADER option, where U-Booot
+provides an EFI environment to the kernel (i.e. replaces UEFI completely but
+provides the same EFI run-time services) is not currently supported on x86.
+
+See README.efi for details of EFI support in U-Boot.
+
+64-bit Support
+--------------
+U-Boot supports booting a 64-bit kernel directly and is able to change to
+64-bit mode to do so. It also supports (with CONFIG_EFI_STUB) booting from
+both 32-bit and 64-bit UEFI. However, U-Boot itself is currently always built
+in 32-bit mode. Some access to the full memory range is provided with
+arch_phys_memset().
+
+The development work to make U-Boot itself run in 64-bit mode has not yet
+been attempted. The best approach would likely be to build a 32-bit SPL
+image for U-Boot, with CONFIG_SPL_BUILD. This could then handle the early CPU
+init in 16-bit and 32-bit mode, running the FSP and any other binaries that
+are needed. Then it could change to 64-bit model and jump to U-Boot proper.
+
+Given U-Boot's extensive 64-bit support this has not been a high priority,
+but it would be a nice addition.
+
 TODO List
 ---------
 - Audio
 - Chrome OS verified boot
+- Support for CONFIG_EFI_LOADER
+- Building U-Boot to run in 64-bit mode
 
 References
 ----------
diff --git a/doc/uImage.FIT/kernel.its b/doc/uImage.FIT/kernel.its
index e668c3f..0aaf47e 100644
--- a/doc/uImage.FIT/kernel.its
+++ b/doc/uImage.FIT/kernel.its
@@ -85,3 +85,7 @@ For x86 a setup node is also required: see x86-fit-boot.txt.
 		};
 	};
 };
+
+Note: the above assumes a 32-bit kernel. To directly boot a 64-bit kernel,
+change both arch values to "x86_64". U-Boot will then change to 64-bit mode
+before booting the kernel (see boot_linux_kernel()).
diff --git a/doc/uImage.FIT/x86-fit-boot.txt b/doc/uImage.FIT/x86-fit-boot.txt
index 61c10ff..02238f9 100644
--- a/doc/uImage.FIT/x86-fit-boot.txt
+++ b/doc/uImage.FIT/x86-fit-boot.txt
@@ -63,9 +63,8 @@ executed.
 Build the kernel
 ----------------
 
-Note: these instructions assume a 32-bit kernel. U-Boot does not currently
-support booting a 64-bit kernel as it has no way of going into 64-bit mode on
-x86.
+Note: these instructions assume a 32-bit kernel. U-Boot also supports directly
+booting a 64-bit kernel by jumping into 64-bit mode first (see below).
 
 You can build the kernel as normal with 'make'. This will create a file called
 'vmlinux'. This is a standard ELF file and you can look at it if you like:
@@ -168,8 +167,9 @@ Create a FIT
 ------------
 
 To create a FIT you will need a source file describing what should go in the
-FIT. See kernel.its for an example for x86. Put this into a file called
-image.its.
+FIT. See kernel.its for an example for x86 and also instructions on setting
+the 'arch' value for booting 64-bit kernels if desired. Put this into a file
+called image.its.
 
 Note that setup is loaded to the special address of 0x90000 (a special address
 you just have to know) and the kernel is loaded to 0x01000000 (the address you
@@ -263,10 +263,6 @@ In the Linux kernel, Documentation/x86/boot.txt defines the boot protocol for
 the kernel including the setup.bin format. This is handled in U-Boot in
 arch/x86/lib/zimage.c and arch/x86/lib/bootm.c.
 
-The procedure for entering 64-bit mode on x86 seems to be described here:
-
-   http://wiki.osdev.org/64-bit_Higher_Half_Kernel_with_GRUB_2
-
 Various files in the same directory as this file describe the FIT format.
 
 
diff --git a/drivers/i2c/intel_i2c.c b/drivers/i2c/intel_i2c.c
index ba80662..a0182dc 100644
--- a/drivers/i2c/intel_i2c.c
+++ b/drivers/i2c/intel_i2c.c
@@ -2,54 +2,290 @@
  * Copyright (c) 2015 Google, Inc
  * Written by Simon Glass <sjg@chromium.org>
  *
+ * SMBus block read/write support added by Stefan Roese:
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
  * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #include <common.h>
 #include <dm.h>
 #include <i2c.h>
+#include <pci.h>
 #include <asm/io.h>
-#include <asm/arch/pch.h>
 
-int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+/* PCI Configuration Space (D31:F3): SMBus */
+#define SMB_BASE		0x20
+#define HOSTC			0x40
+#define  HST_EN			(1 << 0)
+#define SMB_RCV_SLVA		0x09
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT		0x0
+#define SMBHSTCTL		0x2
+#define SMBHSTCMD		0x3
+#define SMBXMITADD		0x4
+#define SMBHSTDAT0		0x5
+#define SMBHSTDAT1		0x6
+#define SMBBLKDAT		0x7
+#define SMBTRNSADD		0x9
+#define SMBSLVDATA		0xa
+#define SMBAUXCTL		0xd
+#define SMLINK_PIN_CTL		0xe
+#define SMBUS_PIN_CTL		0xf
+
+/* I801 Hosts Status register bits */
+#define SMBHSTSTS_BYTE_DONE	0x80
+#define SMBHSTSTS_INUSE_STS	0x40
+#define SMBHSTSTS_SMBALERT_STS	0x20
+#define SMBHSTSTS_FAILED	0x10
+#define SMBHSTSTS_BUS_ERR	0x08
+#define SMBHSTSTS_DEV_ERR	0x04
+#define SMBHSTSTS_INTR		0x02
+#define SMBHSTSTS_HOST_BUSY	0x01
+
+/* I801 Host Control register bits */
+#define SMBHSTCNT_INTREN	0x01
+#define SMBHSTCNT_KILL		0x02
+#define SMBHSTCNT_LAST_BYTE	0x20
+#define SMBHSTCNT_START		0x40
+#define SMBHSTCNT_PEC_EN	0x80	/* ICH3 and later */
+
+/* Auxiliary control register bits, ICH4+ only */
+#define SMBAUXCTL_CRC		1
+#define SMBAUXCTL_E32B		2
+
+#define SMBUS_TIMEOUT	100	/* 100 ms */
+
+struct intel_i2c {
+	u32 base;
+	int running;
+};
+
+static int smbus_wait_until_ready(u32 base)
 {
-	return -ENOSYS;
+	unsigned long ts;
+	u8 byte;
+
+	ts = get_timer(0);
+	do {
+		byte = inb(base + SMBHSTSTAT);
+		if (!(byte & 1))
+			return 0;
+	} while (get_timer(ts) < SMBUS_TIMEOUT);
+
+	return -ETIMEDOUT;
 }
 
-int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr, uint chip_flags)
+static int smbus_wait_until_done(u32 base)
 {
-	return -ENOSYS;
+	unsigned long ts;
+	u8 byte;
+
+	ts = get_timer(0);
+	do {
+		byte = inb(base + SMBHSTSTAT);
+		if (!((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0))
+			return 0;
+	} while (get_timer(ts) < SMBUS_TIMEOUT);
+
+	return -ETIMEDOUT;
 }
 
-int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+static int smbus_block_read(u32 base, u8 dev, u8 *buffer,
+			    int offset, int len)
 {
+	u8 buf_temp[32];
+	int count;
+	int i;
+
+	debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
+	      __func__, __LINE__, dev, offset, len);
+	if (smbus_wait_until_ready(base) < 0)
+		return -ETIMEDOUT;
+
+	/* Setup transaction */
+
+	/* Reset the data buffer index */
+	inb(base + SMBHSTCTL);
+
+	/* Set the device I'm talking too */
+	outb(((dev & 0x7f) << 1) | 1, base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(offset & 0xff, base + SMBHSTCMD);
+	/* Set up for a block read */
+	outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
+	     (base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
+
+	/* Start the command */
+	outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(base) < 0) {
+		printf("SMBUS read transaction timeout (dev=0x%x)\n", dev);
+		return -ETIMEDOUT;
+	}
+
+	count = inb(base + SMBHSTDAT0);
+	debug("%s (%d): count=%d (len=%d)\n", __func__, __LINE__, count, len);
+	if (count == 0) {
+		debug("ERROR: len=0 on read\n");
+		return -EIO;
+	}
+
+	if (count < len) {
+		debug("ERROR: too few bytes read\n");
+		return -EIO;
+	}
+
+	if (count > 32) {
+		debug("ERROR: count=%d too high\n", count);
+		return -EIO;
+	}
+
+	/* Read all available bytes from buffer */
+	for (i = 0; i < count; i++)
+		buf_temp[i] = inb(base + SMBBLKDAT);
+
+	memcpy(buffer, buf_temp, len);
+
+	/* Return results of transaction */
+	if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
+		return -EIO;
+
 	return 0;
 }
 
-static int intel_i2c_probe(struct udevice *dev)
+static int smbus_block_write(u32 base, u8 dev, u8 *buffer,
+			     int offset, int len)
 {
+	int i;
+
+	debug("%s (%d): dev=0x%x offs=0x%x len=0x%x\n",
+	      __func__, __LINE__, dev, offset, len);
+	if (smbus_wait_until_ready(base) < 0)
+		return -ETIMEDOUT;
+
+	/* Setup transaction */
+	/* Set the device I'm talking too */
+	outb(((dev & 0x7f) << 1) & ~0x01, base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(offset, base + SMBHSTCMD);
+	/* Set up for a block write */
+	outb((inb(base + SMBHSTCTL) & (~(0x7) << 2)) | (0x5 << 2),
+	     (base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(base + SMBHSTSTAT), base + SMBHSTSTAT);
+
+	/* Write count in DAT0 register */
+	outb(len, base + SMBHSTDAT0);
+
+	/* Write data bytes... */
+	for (i = 0; i < len; i++)
+		outb(*buffer++, base + SMBBLKDAT);
+
+	/* Start the command */
+	outb((inb(base + SMBHSTCTL) | SMBHSTCNT_START), base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(base) < 0) {
+		printf("SMBUS write transaction timeout (dev=0x%x)\n", dev);
+		return -ETIMEDOUT;
+	}
+
+	/* Return results of transaction */
+	if (!(inb(base + SMBHSTSTAT) & SMBHSTSTS_INTR))
+		return -EIO;
+
+	return 0;
+}
+
+static int intel_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
+{
+	struct intel_i2c *i2c = dev_get_priv(bus);
+	struct i2c_msg *dmsg, *omsg, dummy;
+
+	debug("i2c_xfer: %d messages\n", nmsgs);
+
+	memset(&dummy, 0, sizeof(struct i2c_msg));
+
 	/*
-	 * So far this is just setup code for ivybridge SMbus. When we have
-	 * a full I2C driver this may need to be moved, generalised or made
-	 * dependant on a particular compatible string.
-	 *
-	 * Set SMBus I/O base
+	 * We expect either two messages (one with an offset and one with the
+	 * actucal data) or one message (just data)
 	 */
-	dm_pci_write_config32(dev, SMB_BASE,
-			      SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+	if (nmsgs > 2 || nmsgs == 0) {
+		debug("%s: Only one or two messages are supported", __func__);
+		return -EIO;
+	}
+
+	omsg = nmsgs == 1 ? &dummy : msg;
+	dmsg = nmsgs == 1 ? msg : msg + 1;
+
+	if (dmsg->flags & I2C_M_RD)
+		return smbus_block_read(i2c->base, dmsg->addr, &dmsg->buf[0],
+					omsg->buf[0], dmsg->len);
+	else
+		return smbus_block_write(i2c->base, dmsg->addr, &dmsg->buf[1],
+					 dmsg->buf[0], dmsg->len - 1);
+}
+
+static int intel_i2c_probe_chip(struct udevice *bus, uint chip_addr,
+				uint chip_flags)
+{
+	struct intel_i2c *i2c = dev_get_priv(bus);
+	u8 buf[4];
+
+	return smbus_block_read(i2c->base, chip_addr, buf, 0, 1);
+}
+
+static int intel_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
+{
+	return 0;
+}
+
+static int intel_i2c_probe(struct udevice *dev)
+{
+	struct intel_i2c *priv = dev_get_priv(dev);
+	u32 base;
+
+	/* Save base address from PCI BAR */
+	priv->base = (u32)dm_pci_map_bar(dev, PCI_BASE_ADDRESS_4,
+					 PCI_REGION_IO);
+	base = priv->base;
 
 	/* Set SMBus enable. */
 	dm_pci_write_config8(dev, HOSTC, HST_EN);
 
-	/* Set SMBus I/O space enable. */
-	dm_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+	/* Disable interrupts */
+	outb(inb(base + SMBHSTCTL) & ~SMBHSTCNT_INTREN, base + SMBHSTCTL);
 
-	/* Disable interrupt generation. */
-	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+	/* Set 32-byte data buffer mode */
+	outb(inb(base + SMBAUXCTL) | SMBAUXCTL_E32B, base + SMBAUXCTL);
 
-	/* Clear any lingering errors, so transactions can run. */
-	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-	debug("SMBus controller enabled\n");
+	return 0;
+}
+
+static int intel_i2c_bind(struct udevice *dev)
+{
+	static int num_cards __attribute__ ((section(".data")));
+	char name[20];
+
+	/* Create a unique device name for PCI type devices */
+	if (device_is_on_pci_bus(dev)) {
+		/*
+		 * ToDo:
+		 * Setting req_seq in the driver is probably not recommended.
+		 * But without a DT alias the number is not configured. And
+		 * using this driver is impossible for PCIe I2C devices.
+		 * This can be removed, once a better (correct) way for this
+		 * is found and implemented.
+		 */
+		dev->req_seq = num_cards;
+		sprintf(name, "intel_i2c#%u", num_cards++);
+		device_set_name(dev, name);
+	}
 
 	return 0;
 }
@@ -70,5 +306,17 @@ U_BOOT_DRIVER(intel_i2c) = {
 	.id	= UCLASS_I2C,
 	.of_match = intel_i2c_ids,
 	.ops	= &intel_i2c_ops,
+	.priv_auto_alloc_size = sizeof(struct intel_i2c),
+	.bind	= intel_i2c_bind,
 	.probe	= intel_i2c_probe,
 };
+
+static struct pci_device_id intel_smbus_pci_supported[] = {
+	/* Intel BayTrail SMBus on the PCI bus */
+	{ PCI_VDEVICE(INTEL, 0x0f12) },
+	/* Intel IvyBridge (Panther Point PCH) SMBus on the PCI bus */
+	{ PCI_VDEVICE(INTEL, 0x1e22) },
+	{},
+};
+
+U_BOOT_PCI_DEVICE(intel_i2c, intel_smbus_pci_supported);
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4af1cbf..8990489 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -90,6 +90,14 @@ config MXC_OCOTP
 	  Programmable memory pages that are stored on the some
 	  Freescale i.MX processors.
 
+config NUVOTON_NCT6102D
+	bool "Enable Nuvoton NCT6102D Super I/O driver"
+	help
+	  If you say Y here, you will get support for the Nuvoton
+	  NCT6102D Super I/O driver. This can be used to enable or
+	  disable the legacy UART, the watchdog or other devices
+	  in the Nuvoton Super IO chips on X86 platforms.
+
 config PWRSEQ
 	bool "Enable power-sequencing drivers"
 	depends on DM
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index dac9d10..c0e5f03 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
+obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_PDSP188x) += pdsp188x.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
diff --git a/drivers/misc/nuvoton_nct6102d.c b/drivers/misc/nuvoton_nct6102d.c
new file mode 100644
index 0000000..ced70f1
--- /dev/null
+++ b/drivers/misc/nuvoton_nct6102d.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <nuvoton_nct6102d.h>
+#include <asm/io.h>
+#include <asm/pnp_def.h>
+
+static void superio_outb(int reg, int val)
+{
+	outb(reg, NCT_EFER);
+	outb(val, NCT_EFDR);
+}
+
+static inline int superio_inb(int reg)
+{
+	outb(reg, NCT_EFER);
+	return inb(NCT_EFDR);
+}
+
+static int superio_enter(void)
+{
+	outb(NCT_ENTRY_KEY, NCT_EFER); /* Enter extended function mode */
+	outb(NCT_ENTRY_KEY, NCT_EFER); /* Again according to manual */
+
+	return 0;
+}
+
+static void superio_select(int ld)
+{
+	superio_outb(NCT_LD_SELECT_REG, ld);
+}
+
+static void superio_exit(void)
+{
+	outb(NCT_EXIT_KEY, NCT_EFER); /* Leave extended function mode */
+}
+
+/*
+ * The Nuvoton NCT6102D starts per default after reset with both,
+ * the internal watchdog and the internal legacy UART enabled. This
+ * code provides a function to disable the watchdog.
+ */
+int nct6102d_wdt_disable(void)
+{
+	superio_enter();
+	/* Select logical device for WDT */
+	superio_select(NCT6102D_LD_WDT);
+	superio_outb(NCT6102D_WDT_TIMEOUT, 0x00);
+	superio_exit();
+
+	return 0;
+}
diff --git a/fs/cbfs/cbfs.c b/fs/cbfs/cbfs.c
index 95a48a4..6e1107d 100644
--- a/fs/cbfs/cbfs.c
+++ b/fs/cbfs/cbfs.c
@@ -97,8 +97,8 @@ static int file_cbfs_next_file(u8 *start, u32 size, u32 align,
 		}
 
 		swap_file_header(&header, fileHeader);
-		if (header.offset < sizeof(const struct cbfs_cachenode *) ||
-				header.offset > header.len) {
+		if (header.offset < sizeof(struct cbfs_fileheader) ||
+		    header.offset > header.len) {
 			file_cbfs_result = CBFS_BAD_FILE;
 			return -1;
 		}
@@ -106,9 +106,9 @@ static int file_cbfs_next_file(u8 *start, u32 size, u32 align,
 		newNode->type = header.type;
 		newNode->data = start + header.offset;
 		newNode->data_length = header.len;
-		name_len = header.offset - sizeof(struct cbfs_cachenode *);
+		name_len = header.offset - sizeof(struct cbfs_fileheader);
 		newNode->name = (char *)fileHeader +
-				sizeof(struct cbfs_cachenode *);
+				sizeof(struct cbfs_fileheader);
 		newNode->name_length = name_len;
 		newNode->checksum = header.checksum;
 
diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h
index 4c37d5e..652e073 100644
--- a/include/configs/conga-qeval20-qa3-e3845.h
+++ b/include/configs/conga-qeval20-qa3-e3845.h
@@ -15,6 +15,7 @@
 
 #define CONFIG_SYS_MONITOR_LEN		(1 << 20)
 #define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_BOARD_LATE_INIT
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_ARCH_MISC_INIT
 
@@ -41,23 +42,24 @@
 #define CONFIG_CMD_BMP
 
 #define CONFIG_ENV_SECT_SIZE		0x1000
-#define CONFIG_ENV_OFFSET		0x007fe000
+#define CONFIG_ENV_OFFSET		0x006ef000
 
 #undef CONFIG_BOOTARGS
 #undef CONFIG_BOOTCOMMAND
 
 #define CONFIG_BOOTARGS		\
-	"root=/dev/sda1 ro quiet"
+	"root=/dev/sda2 ro quiet"
 #define CONFIG_BOOTCOMMAND	\
-	"load scsi 0:1 03000000 /boot/vmlinuz-4.2.0-26-generic;" \
-	"load scsi 0:1 04000000 /boot/initrd.img-4.2.0-26-generic;" \
+	"load scsi 0:2 03000000 /boot/vmlinuz-${kernel-ver}-generic;"	\
+	"load scsi 0:2 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
 	"run boot"
 
 #undef CONFIG_EXTRA_ENV_SETTINGS
 #define CONFIG_EXTRA_ENV_SETTINGS				\
+	"kernel-ver=4.4.0-22\0"					\
 	"boot=zboot 03000000 0 04000000 ${filesize}\0"		\
 	"upd_uboot=tftp 100000 conga/u-boot.rom;"		\
-		"sf probe;sf update 100000 0 7fe000\0"
+		"sf probe;sf update 100000 0 800000;saveenv\0"
 
 #define CONFIG_PREBOOT
 
diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h
new file mode 100644
index 0000000..23d8a0a
--- /dev/null
+++ b/include/configs/dfi-bt700.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/x86-common.h>
+
+#define CONFIG_SYS_MONITOR_LEN		(1 << 20)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#ifndef CONFIG_INTERNAL_UART
+/* Use BayTrail internal HS UART which is memory-mapped */
+#undef  CONFIG_SYS_NS16550_PORT_MAPPED
+#endif
+
+#define CONFIG_PCI_PNP
+
+#define CONFIG_STD_DEVICES_SETTINGS     "stdin=serial\0" \
+					"stdout=serial\0" \
+					"stderr=serial\0"
+
+#define CONFIG_SCSI_DEV_LIST		\
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA}, \
+	{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_VALLEYVIEW_SATA_ALT}
+
+#define CONFIG_MMC
+#define CONFIG_SDHCI
+#define CONFIG_GENERIC_MMC
+#define CONFIG_MMC_SDMA
+
+#undef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
+
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_USB_ETHER_SMSC95XX
+#define CONFIG_USB_ETHER_MCS7830
+#define CONFIG_USB_ETHER_RTL8152
+
+#define VIDEO_IO_OFFSET				0
+#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_CMD_BMP
+
+#define CONFIG_ENV_SECT_SIZE		0x1000
+#define CONFIG_ENV_OFFSET		0x006ef000
+
+#undef CONFIG_BOOTARGS
+#undef CONFIG_BOOTCOMMAND
+
+#define CONFIG_BOOTARGS		\
+	"root=/dev/sda1 ro quiet"
+#define CONFIG_BOOTCOMMAND	\
+	"load scsi 0:1 03000000 /boot/vmlinuz-${kernel-ver}-generic;"	\
+	"load scsi 0:1 04000000 /boot/initrd.img-${kernel-ver}-generic;" \
+	"run boot"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS				\
+	"kernel-ver=4.4.0-24\0"					\
+	"boot=zboot 03000000 0 04000000 ${filesize}\0"		\
+	"upd_uboot=usb reset;tftp 100000 dfi/u-boot.rom;"	\
+		"sf probe;sf update 100000 0 800000;saveenv\0"
+
+#define CONFIG_PREBOOT
+
+#endif	/* __CONFIG_H */
diff --git a/include/nuvoton_nct6102d.h b/include/nuvoton_nct6102d.h
new file mode 100644
index 0000000..a122550
--- /dev/null
+++ b/include/nuvoton_nct6102d.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2016 Stefan Roese <sr@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _NUVOTON_NCT6102D_H_
+#define _NUVOTON_NCT6102D_H_
+
+/* I/O address of Nuvoton Super IO chip */
+#define NCT6102D_IO_PORT	0x4e
+
+/* Extended Function Enable Registers */
+#define NCT_EFER (NCT6102D_IO_PORT + 0)
+/* Extended Function Index Register (same as EFER) */
+#define NCT_EFIR (NCT6102D_IO_PORT + 0)
+/* Extended Function Data Register */
+#define NCT_EFDR (NCT_EFIR + 1)
+
+#define NCT_LD_SELECT_REG	0x07
+
+/* Logical device number */
+#define NCT6102D_LD_UARTA	0x02
+#define NCT6102D_LD_WDT		0x08
+
+#define NCT6102D_UARTA_ENABLE	0x30
+#define NCT6102D_WDT_TIMEOUT	0xf1
+
+#define NCT_ENTRY_KEY		0x87
+#define NCT_EXIT_KEY		0xaa
+
+int nct6102d_wdt_disable(void);
+
+#endif /* _NUVOTON_NCT6102D_H_ */