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authorPrabhakar Kushwaha <prabhakar@freescale.com>2014-03-08 16:45:04 +0530
committerYork Sun <yorksun@freescale.com>2014-04-22 17:58:47 -0700
commit6b50f62cc4df7e2961fb45980cf91bb424ee263b (patch)
tree089b64c9c4d6bf24e0e030bdf5668b330658395b
parent59ff5d3306b9ac6d3afa0a249e17d8c14519e0cb (diff)
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board/b4860qds:Slow MDC clock to comply IEEE specs in PBI config
The MDC generate by default value of MDIO_CLK_DIV is too high i.e. higher than 2.5 MHZ. It violates the IEEE specs. So Slow MDC clock to comply IEEE specs Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
-rw-r--r--board/freescale/b4860qds/b4_pbi.cfg3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/freescale/b4860qds/b4_pbi.cfg b/board/freescale/b4860qds/b4_pbi.cfg
index 57b726e..05377ba 100644
--- a/board/freescale/b4860qds/b4_pbi.cfg
+++ b/board/freescale/b4860qds/b4_pbi.cfg
@@ -22,6 +22,9 @@
09110024 00100008
09110028 00100008
0911002c 00100008
+#slowing down the MDC clock to make it <= 2.5 MHZ
+094fc030 00008148
+094fd030 00008148
#Flush PBL data
09138000 00000000
091380c0 00000000