diff options
| author | Ye Li <ye.li@nxp.com> | 2017-03-15 16:53:31 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-05 17:24:31 +0800 |
| commit | 5a69ddb7e9886e082da42ddf673415702975ee60 (patch) | |
| tree | 647445422a61332d8a2b0ff4b934081666a3f425 | |
| parent | cafc860907a408156a43fa20169dfc187648618e (diff) | |
| download | u-boot-imx-5a69ddb7e9886e082da42ddf673415702975ee60.zip u-boot-imx-5a69ddb7e9886e082da42ddf673415702975ee60.tar.gz u-boot-imx-5a69ddb7e9886e082da42ddf673415702975ee60.tar.bz2 | |
MLK-13450-16 fsl_qspi: Update changes for mx7ulp
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.
Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 25 |
1 files changed, 24 insertions, 1 deletions
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index b1b5770..2d1338f 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -402,6 +402,7 @@ static inline void qspi_ahb_read(struct fsl_qspi_priv *priv, u8 *rxbuf, int len) qspi_write32(priv->flags, ®s->mcr, mcr_reg); } +#ifndef CONFIG_MX7ULP static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) { u32 reg, reg2; @@ -424,6 +425,7 @@ static void qspi_enable_ddr_mode(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->mcr, reg); } +#endif /* * There are two different ways to read out the data from the flash: @@ -446,8 +448,13 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->buf0cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, ®s->buf1cr, QSPI_BUFXCR_INVALID_MSTRID); qspi_write32(priv->flags, ®s->buf2cr, QSPI_BUFXCR_INVALID_MSTRID); +#ifdef CONFIG_MX7ULP + qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | + (0x10 << QSPI_BUF3CR_ADATSZ_SHIFT)); +#else qspi_write32(priv->flags, ®s->buf3cr, QSPI_BUF3CR_ALLMST_MASK | (0x80 << QSPI_BUF3CR_ADATSZ_SHIFT)); +#endif /* We only use the buffer3 */ qspi_write32(priv->flags, ®s->buf0ind, 0); @@ -461,8 +468,10 @@ static void qspi_init_ahb_read(struct fsl_qspi_priv *priv) qspi_write32(priv->flags, ®s->bfgencr, SEQID_FAST_READ << QSPI_BFGENCR_SEQID_SHIFT); +#ifndef CONFIG_MX7ULP /*Enable DDR Mode*/ qspi_enable_ddr_mode(priv); +#endif } #endif @@ -679,7 +688,7 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 *txbuf, u32 len) total += 1; } -#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL) +#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7ULP) /* iMX7D and MX6UL TXFIFO must be at least 16 bytes*/ for (; total < 4; total++) qspi_write32(priv->flags, ®s->tbdr, 0); @@ -924,6 +933,18 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, QSPI_SMPR_FSPHS_MASK | QSPI_SMPR_HSENA_MASK), 0); total_size = FSL_QSPI_FLASH_SIZE * FSL_QSPI_FLASH_NUM; + +#if defined(CONFIG_MX7ULP) + /* + * mx7ulp QSPI controller does not support parallel mode, it only has port A. + * To support dual die flash and single die flash, we set flash 1 size to CS0 area, + * set flash2 size to CS1 area. + */ + qspi_write32(qspi->priv.flags, ®s->sfa1ad, + FSL_QSPI_FLASH_SIZE | amba_bases[bus]); + qspi_write32(qspi->priv.flags, ®s->sfa2ad, + total_size | amba_bases[bus]); +#else /* * Any read access to non-implemented addresses will provide * undefined results. @@ -942,6 +963,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, total_size | amba_bases[bus]); qspi_write32(qspi->priv.flags, ®s->sfb2ad, total_size | amba_bases[bus]); +#endif qspi_set_lut(&qspi->priv); @@ -1219,6 +1241,7 @@ static const struct udevice_id fsl_qspi_ids[] = { { .compatible = "fsl,imx6sx-qspi" }, { .compatible = "fsl,imx6ul-qspi" }, { .compatible = "fsl,imx7d-qspi" }, + { .compatible = "fsl,imx7ulp-qspi" }, { } }; |