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authorFabio Estevam <festevam@gmail.com>2011-06-05 14:56:02 +0000
committerStefano Babic <sbabic@denx.de>2011-06-06 09:35:25 +0200
commit4e37731a27faeba57e4814954544ce18324ae259 (patch)
tree0fc2fe12352ab725f1ac7a438d7272451d4f3a65
parent4ac2e2d69fb028c7bd749a07346820a4fd38f65a (diff)
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mx31litekit: Fix boot with the new relocation scheme.
imx31_litekit has been converted to the new relocation scheme, but it does not boot. Make the boot functional by using board_early_init_f . Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
-rw-r--r--board/logicpd/imx31_litekit/imx31_litekit.c17
-rw-r--r--include/configs/imx31_litekit.h1
2 files changed, 12 insertions, 6 deletions
diff --git a/board/logicpd/imx31_litekit/imx31_litekit.c b/board/logicpd/imx31_litekit/imx31_litekit.c
index 2ed742f..bf635c3 100644
--- a/board/logicpd/imx31_litekit/imx31_litekit.c
+++ b/board/logicpd/imx31_litekit/imx31_litekit.c
@@ -29,21 +29,21 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init (void)
+int dram_init(void)
{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
-
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
return 0;
}
-void
-dram_init_banksize (void)
+void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
}
-int board_init (void)
+int board_early_init_f(void)
{
__REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
__REG(CSCR_L(0)) = 0xa0330d01;
@@ -71,6 +71,11 @@ int board_init (void)
/* start SPI2 clock */
__REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
+ return 0;
+}
+
+int board_init(void)
+{
gd->bd->bi_arch_number = MACH_TYPE_MX31LITE; /* board id for linux */
gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 9405f56..7ee7076 100644
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -145,6 +145,7 @@
#define CONFIG_NR_DRAM_BANKS 1
#define PHYS_SDRAM_1 CSD0_BASE
#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_SYS_SDRAM_BASE CSD0_BASE
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR