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| author | Simon Glass <sjg@chromium.org> | 2016-01-17 16:11:10 -0700 |
|---|---|---|
| committer | Bin Meng <bmeng.cn@gmail.com> | 2016-01-24 12:07:19 +0800 |
| commit | 4acc83d437da7a40e7c2b1874eaba23273ec6bc2 (patch) | |
| tree | 5ff12c47ee88240dac8878c8da66892f747323f5 | |
| parent | 7282672d298905088fb3c7c0a049d7d7d31cb8b4 (diff) | |
| download | u-boot-imx-4acc83d437da7a40e7c2b1874eaba23273ec6bc2.zip u-boot-imx-4acc83d437da7a40e7c2b1874eaba23273ec6bc2.tar.gz u-boot-imx-4acc83d437da7a40e7c2b1874eaba23273ec6bc2.tar.bz2 | |
x86: ivybridge: Set up the LPC device using driver model
Find the LPC device in arch_cpu_init_dm() as a first step to converting
this code to use driver model. Probing the LPC will probe its parent (the
PCH) automatically, so make sure that probing the PCH does nothing before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| -rw-r--r-- | arch/x86/cpu/ivybridge/bd82x6x.c | 3 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/cpu.c | 6 | ||||
| -rw-r--r-- | arch/x86/cpu/ivybridge/lpc.c | 6 | ||||
| -rw-r--r-- | arch/x86/dts/chromebook_link.dts | 1 |
4 files changed, 15 insertions, 1 deletions
diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index c000aca..72f2ed4 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -65,6 +65,9 @@ static int bd82x6x_probe(struct udevice *dev) int sata_node, gma_node; int ret; + if (!(gd->flags & GD_FLG_RELOC)) + return 0; + hose = pci_bus_to_hose(0); lpc_enable(PCH_LPC_DEV); lpc_init(hose, PCH_LPC_DEV); diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 343bfb4..6ffc843 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -126,7 +126,7 @@ int arch_cpu_init_dm(void) { const void *blob = gd->fdt_blob; struct pci_controller *hose; - struct udevice *bus; + struct udevice *bus, *dev; int node; int ret; @@ -141,6 +141,10 @@ int arch_cpu_init_dm(void) /* TODO(sjg@chromium.org): Get rid of gd->hose */ gd->hose = hose; + ret = uclass_first_device(UCLASS_LPC, &dev); + if (!dev) + return -ENODEV; + node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH); if (node < 0) return -ENOENT; diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index af5d4a8..51a4073 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -559,6 +559,11 @@ void lpc_enable(pci_dev_t dev) setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF); } +static int bd82x6x_lpc_probe(struct udevice *dev) +{ + return 0; +} + static const struct udevice_id bd82x6x_lpc_ids[] = { { .compatible = "intel,bd82x6x-lpc" }, { } @@ -568,4 +573,5 @@ U_BOOT_DRIVER(bd82x6x_lpc_drv) = { .name = "lpc", .id = UCLASS_LPC, .of_match = bd82x6x_lpc_ids, + .probe = bd82x6x_lpc_probe, }; diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts index a5c5dc1..d5c5bfd 100644 --- a/arch/x86/dts/chromebook_link.dts +++ b/arch/x86/dts/chromebook_link.dts @@ -223,6 +223,7 @@ compatible = "intel,bd82x6x-lpc"; #address-cells = <1>; #size-cells = <0>; + u-boot,dm-pre-reloc; cros-ec@200 { compatible = "google,cros-ec"; reg = <0x204 1 0x200 1 0x880 0x80>; |