MLK-14445-2 mx7ulp_evk: Add QSPI flash support

Porting the QSPI flash board support from v2016.03, and convert to use
DM QSPI driver.
Since we need to support QSPI at default in u-boot, change the default
DTS file to qspi enabled DTS.

Signed-off-by: Ye Li <ye.li@nxp.com>

7 files changed, 111 insertions, 3 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 1b8b327..3569078 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -375,7 +375,8 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 		imx7d-19x19-lpddr2-arm2.dtb \
 		imx7d-19x19-lpddr3-arm2.dtb
 
-dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
+		imx7ulp-evk-qspi.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
diff --git a/arch/arm/dts/imx7ulp-evk-qspi.dts b/arch/arm/dts/imx7ulp-evk-qspi.dts
new file mode 100644
index 0000000..450ea0e
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-evk-qspi.dts
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7ulp-evk.dts"
+
+&qspi1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_qspi1_1>;
+	status = "okay";
+
+	flash0: mx25r6435f@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "macronix,mx25r6435f";
+		spi-max-frequency = <29000000>;
+	};
+};
+
+&iomuxc {
+	status = "okay";
+};
+
+&iomuxc {
+	imx7ulp-evk {
+		pinctrl_qspi1_1: qspi1grp_1 {
+			fsl,pins = <
+				ULP1_PAD_PTB7_LLWU0_P11__QSPIA_SS1_B    0x43 /* SS1 */
+				ULP1_PAD_PTB8__QSPIA_SS0_B              0x43 /* SS0 */
+				ULP1_PAD_PTB15__QSPIA_SCLK              0x43 /* SCLK */
+				ULP1_PAD_PTB9_LLWU0_P12__QSPIA_DQS      0x43 /* DQS */
+				ULP1_PAD_PTB16_LLWU0_P14__QSPIA_DATA3   0x43 /* D3 */
+				ULP1_PAD_PTB17__QSPIA_DATA2             0x43 /* D2 */
+				ULP1_PAD_PTB18__QSPIA_DATA1             0x43 /* D1 */
+				ULP1_PAD_PTB19_LLWU0_P15__QSPIA_DATA0   0x43 /* D0 */
+			>;
+		};
+	};
+};
+
diff --git a/arch/arm/dts/imx7ulp.dtsi b/arch/arm/dts/imx7ulp.dtsi
index 5497734..37f1308 100644
--- a/arch/arm/dts/imx7ulp.dtsi
+++ b/arch/arm/dts/imx7ulp.dtsi
@@ -31,6 +31,7 @@
 		i2c1 = &lpi2c5;
 		i2c2 = &lpi2c6;
 		i2c3 = &lpi2c7;
+		spi0 = &qspi1;
 	};
 
 	cpus {
diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
index 3618715..d6c27db 100644
--- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c
+++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c
@@ -13,6 +13,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
 
 int dram_init(void)
 {
@@ -32,6 +33,36 @@ static void setup_iomux_uart(void)
 					 ARRAY_SIZE(lpuart4_pads));
 }
 
+#ifdef CONFIG_FSL_QSPI
+#ifndef CONFIG_DM_SPI
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+};
+#endif
+
+int board_qspi_init(void)
+{
+	u32 val;
+#ifndef CONFIG_DM_SPI
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+#endif
+
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+	return 0;
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
@@ -44,5 +75,9 @@ int board_init(void)
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
 	return 0;
 }
diff --git a/configs/mx7ulp_evk_defconfig b/configs/mx7ulp_evk_defconfig
index ea2a0cf..c556a88 100644
--- a/configs/mx7ulp_evk_defconfig
+++ b/configs/mx7ulp_evk_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_MX7ULP=y
 CONFIG_TARGET_MX7ULP_EVK=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
@@ -23,3 +23,9 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/configs/mx7ulp_evk_plugin_defconfig b/configs/mx7ulp_evk_plugin_defconfig
index d4c36d9..f7e6652 100644
--- a/configs/mx7ulp_evk_plugin_defconfig
+++ b/configs/mx7ulp_evk_plugin_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_MX7ULP=y
 CONFIG_TARGET_MX7ULP_EVK=y
 CONFIG_USE_IMXIMG_PLUGIN=y
-CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk"
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-evk-qspi"
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_evk/imximage.cfg"
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_I2C=y
@@ -24,3 +24,9 @@ CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_CMD_GPIO=y
+CONFIG_CMD_SF=y
+CONFIG_FSL_QSPI=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_MACRONIX=y
diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h
index cc3f0bb..d3cb257 100644
--- a/include/configs/mx7ulp_evk.h
+++ b/include/configs/mx7ulp_evk.h
@@ -195,6 +195,19 @@
 #define CONFIG_CMD_CACHE
 #endif
 
+/* QSPI configs */
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS           0
+#define CONFIG_SF_DEFAULT_CS            0
+#define CONFIG_SF_DEFAULT_SPEED         40000000
+#define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
+#define FSL_QSPI_FLASH_NUM              1
+#define FSL_QSPI_FLASH_SIZE             SZ_8M
+#define QSPI0_BASE_ADDR                 0x410A5000
+#define QSPI0_AMBA_BASE                 0xC0000000
+#endif
+
 #define CONFIG_OF_SYSTEM_SETUP
 
 #endif	/* __CONFIG_H */