summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorStephen Warren <swarren@nvidia.com>2016-07-18 17:01:51 -0600
committerTom Warren <twarren@nvidia.com>2016-07-21 09:31:30 -0700
commit2a5f7f20747637cd1f94d4accfd7caa99a7c6035 (patch)
tree713bbf545a37930b51b731d925dfe60df74f1a82
parent0e2b5350d9523c9b2dca57b98c89f031691d23e3 (diff)
downloadu-boot-imx-2a5f7f20747637cd1f94d4accfd7caa99a7c6035.zip
u-boot-imx-2a5f7f20747637cd1f94d4accfd7caa99a7c6035.tar.gz
u-boot-imx-2a5f7f20747637cd1f94d4accfd7caa99a7c6035.tar.bz2
ARM: tegra: pick up actual memory size
On Tegra186, U-Boot is booted by the binary firmware as if it were a Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address of that DTB, and parse the /memory/reg property to determine the actual RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use. Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion that U-Boot use that DTB as its control DTB. I don't believe that would work well, so I do not plan to put any effort into this. By default the FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT bindings. U-Boot aims to use only upstreamed DT bindings, or as close as it can get. Replacing this DTB with a DTB using upstream bindings is physically quite easy; simply replace the content of one of the GPT partitions on the eMMC. However, the binary FW at least partially relies on the existence/content of some nodes in the DTB, and that requires the DTB to be written according to downstream bindings. Equally, if U-Boot continues to use appended DTBs built from its own source tree, as it does for all other Tegra platforms, development and deployment is much easier. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
-rw-r--r--arch/arm/mach-tegra/board186.c12
-rw-r--r--arch/arm/mach-tegra/tegra186/Makefile2
-rw-r--r--arch/arm/mach-tegra/tegra186/nvtboot_ll.S20
-rw-r--r--arch/arm/mach-tegra/tegra186/nvtboot_mem.c88
4 files changed, 110 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/board186.c b/arch/arm/mach-tegra/board186.c
index f4b6152..876ccba 100644
--- a/arch/arm/mach-tegra/board186.c
+++ b/arch/arm/mach-tegra/board186.c
@@ -11,12 +11,6 @@
DECLARE_GLOBAL_DATA_PTR;
-int dram_init(void)
-{
- gd->ram_size = (1.5 * 1024 * 1024 * 1024);
- return 0;
-}
-
int board_early_init_f(void)
{
return 0;
@@ -32,12 +26,6 @@ int board_late_init(void)
return 0;
}
-void dram_init_banksize(void)
-{
- gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
- gd->bd->bi_dram[0].size = gd->ram_size;
-}
-
void pad_init_mmc(struct mmc_host *host)
{
}
diff --git a/arch/arm/mach-tegra/tegra186/Makefile b/arch/arm/mach-tegra/tegra186/Makefile
index 188b097..033d600 100644
--- a/arch/arm/mach-tegra/tegra186/Makefile
+++ b/arch/arm/mach-tegra/tegra186/Makefile
@@ -3,3 +3,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-y += ../board186.o
+obj-y += nvtboot_ll.o
+obj-y += nvtboot_mem.o
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_ll.S b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
new file mode 100644
index 0000000..1eab890
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_ll.S
@@ -0,0 +1,20 @@
+/*
+ * Save nvtboot-related boot-time CPU state
+ *
+ * (C) Copyright 2015-2016 NVIDIA Corporation <www.nvidia.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+
+.globl nvtboot_boot_x0
+nvtboot_boot_x0:
+ .dword 0
+
+ENTRY(save_boot_params)
+ adr x8, nvtboot_boot_x0
+ str x0, [x8]
+ b save_boot_params_ret
+ENDPROC(save_boot_params)
diff --git a/arch/arm/mach-tegra/tegra186/nvtboot_mem.c b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
new file mode 100644
index 0000000..37dd8d4
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra186/nvtboot_mem.c
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <fdt_support.h>
+#include <fdtdec.h>
+#include <asm/arch/tegra.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern unsigned long nvtboot_boot_x0;
+
+/*
+ * A parsed version of /memory/reg from the DTB that is passed to U-Boot in x0.
+ *
+ * We only support up to two banks since that's all the binary bootloader
+ * ever sets. We assume bank 0 is RAM below 4G and bank 1 is RAM above 4G.
+ * This is all a fairly safe assumption, since the L4T kernel makes the same
+ * assumptions, so the bootloader is unlikely to change.
+ *
+ * This is written to before relocation, and hence cannot be in .bss, since
+ * .bss overlaps the DTB that's appended to the U-Boot binary. The initializer
+ * forces this into .data and avoids this issue. This also has the nice side-
+ * effect of the content being valid after relocation.
+ */
+static struct {
+ u64 start;
+ u64 size;
+} ram_banks[2] = {{1}};
+
+int dram_init(void)
+{
+ unsigned int na, ns;
+ const void *nvtboot_blob = (void *)nvtboot_boot_x0;
+ int node, len, i;
+ const u32 *prop;
+
+ memset(ram_banks, 0, sizeof(ram_banks));
+
+ na = fdtdec_get_uint(nvtboot_blob, 0, "#address-cells", 2);
+ ns = fdtdec_get_uint(nvtboot_blob, 0, "#size-cells", 2);
+
+ node = fdt_path_offset(nvtboot_blob, "/memory");
+ if (node < 0) {
+ error("Can't find /memory node in nvtboot DTB");
+ hang();
+ }
+ prop = fdt_getprop(nvtboot_blob, node, "reg", &len);
+ if (!prop) {
+ error("Can't find /memory/reg property in nvtboot DTB");
+ hang();
+ }
+
+ len /= (na + ns);
+ if (len > ARRAY_SIZE(ram_banks))
+ len = ARRAY_SIZE(ram_banks);
+
+ gd->ram_size = 0;
+ for (i = 0; i < len; i++) {
+ ram_banks[i].start = of_read_number(prop, na);
+ prop += na;
+ ram_banks[i].size = of_read_number(prop, ns);
+ prop += ns;
+ gd->ram_size += ram_banks[i].size;
+ }
+
+ return 0;
+}
+
+extern unsigned long nvtboot_boot_x0;
+
+void dram_init_banksize(void)
+{
+ int i;
+
+ for (i = 0; i < 2; i++) {
+ gd->bd->bi_dram[i].start = ram_banks[i].start;
+ gd->bd->bi_dram[i].size = ram_banks[i].size;
+ }
+}
+
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return ram_banks[0].start + ram_banks[0].size;
+}