IGEP0146: Ethernet Clock Rework

IMXUL now provides 50 MHz clock to LAN8720AI

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

1 files changed, 23 insertions, 18 deletions

diff --git a/board/isee/igep0146/igep0146.c b/board/isee/igep0146/igep0146.c
index 8b4fefd..a7d52a8 100644
--- a/board/isee/igep0146/igep0146.c
+++ b/board/isee/igep0146/igep0146.c
@@ -55,10 +55,13 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_HIGH   |                                   \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
-#define ENET_TR_CTRL  ( PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | PAD_CTL_SPEED_HIGH  | \
+#define ENET_TX_CTRL  ( PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | PAD_CTL_SPEED_HIGH  | \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST)
+
+#define ENET_RX_CTRL  ( PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | PAD_CTL_SPEED_HIGH  | \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
 
-#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_DISABLE | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 
 #define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
 	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
@@ -121,11 +124,11 @@ static iomux_v3_cfg_t const enet1_pads[] = {
 	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
 	
-	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_TR_CTRL),
-	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_TR_CTRL),
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_TX_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_TX_CTRL),
 
-	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_TR_CTRL),
-	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_TR_CTRL),
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_RX_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_RX_CTRL),
 
 	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
@@ -273,25 +276,24 @@ void mu_reset_phy(void)
 	/* Reset LAN8720 PHY */
 	gpio_request(ETH_PHY_RESET, "LAN8720 PHY RST");
 	gpio_direction_output(ETH_PHY_RESET , 0);
-	mdelay(2);
+	mdelay(10);
 	gpio_set_value(ETH_PHY_RESET, 1);
-	mdelay(2);
-
+	mdelay(10);
 }
 
 static int setup_phy(void)
 {
 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
-
-	/* clear gpr1[17], set gpr1[13] to select external anatop clock for ENET1 (actually provided by PHY) */
-	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
-
-	/* clear gpr1[17], set gpr1[14] to select external anatop clock for ENET2 (actually provided by PHY) */
-	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
+	int ret;
+	int fec_id = 0;
 	
-	//enable_fec_anatop_clock(0, ENET_50MHZ);
-	//enable_enet_clk(1);
+	/* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]*/
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
+	ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
+	if (ret)
+		return ret;
 
+	enable_enet_clk(1);
 	return 0;
 
 }
@@ -302,7 +304,6 @@ int board_eth_init(bd_t *bis)
 	int ret = 0 ;
 	eth_setenv_enetaddr("ethaddr", get_mac_address());
 	setup_iomux_enet();
-	setup_phy();
 	mu_reset_phy();
 
 	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
@@ -427,6 +428,10 @@ int board_init(void)
 		}
 	}
 
+#ifdef	CONFIG_FEC_MXC
+	setup_phy();
+#endif
+
 	return 0;	
 }