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authorPeter Korsgaard <peter.korsgaard@barco.com>2012-10-17 09:20:46 +0000
committerTom Rini <trini@ti.com>2012-10-25 11:30:50 -0700
commit22cbeed454087ffa6ae6e56880bfff125497619b (patch)
treeacb585041b9fde670a748f1763c2c398666248c8
parent8f1fae26a7fb4c0c2897f2f086fe8a3e1da58a9a (diff)
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omap3_spi: introduce CONFIG_OMAP3_SPI_D0_D1_SWAPPED
D0/D1 Swapped or not is a board property, not anything specific to the am33xx SoC, so add a custom define for it. At the same time correct the bit handling for the swapped mode (DPE0 should be cleared and SI/DPE1 set). Signed-off-by: Peter Korsgaard <peter.korsgaard@barco.com>
-rw-r--r--drivers/spi/omap3_spi.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c
index e40a632..6791a7e 100644
--- a/drivers/spi/omap3_spi.c
+++ b/drivers/spi/omap3_spi.c
@@ -173,14 +173,13 @@ int spi_claim_bus(struct spi_slave *slave)
/* standard 4-wire master mode: SCK, MOSI/out, MISO/in, nCS
* REVISIT: this controller could support SPI_3WIRE mode.
*/
-#ifdef CONFIG_AM33XX
+#ifdef CONFIG_OMAP3_SPI_D0_D1_SWAPPED
/*
- * The reference design on AM33xx has D0 and D1 wired up opposite
- * of how it has been done on previous platforms. We assume that
- * custom hardware will also follow this convention.
+ * Some boards have D0 wired as MOSI / D1 as MISO instead of
+ * The normal D0 as MISO / D1 as MOSI.
*/
- conf &= OMAP3_MCSPI_CHCONF_DPE0;
- conf |= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
+ conf &= ~OMAP3_MCSPI_CHCONF_DPE0;
+ conf |= OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1;
#else
conf &= ~(OMAP3_MCSPI_CHCONF_IS|OMAP3_MCSPI_CHCONF_DPE1);
conf |= OMAP3_MCSPI_CHCONF_DPE0;