Merge branch 'master' of /home/wd/git/u-boot/custodians

2 files changed, 25 insertions, 18 deletions

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 07fbb0e..e880c28 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void)
 	/* Set PLL clock receiver to LVPECL */
 	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
 
-	if (check_error())
+	if (check_error()) {
+		printf("ERROR: failed to set PCIe reference clock receiver --"
+			"PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
+
 		return -1;
+	}
+
+	/* Did resistance calibration work? */
+	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
+		printf("ERROR: PCIe resistance calibration failed --"
+			"PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
 
-	if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
-	{
-		printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
-		       SDR_READ(PESDR0_PLLLCT2));
 		return -1;
 	}
 	/* De-assert reset of PCIe PLL, wait for lock */
 	SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
-	udelay(3);
+	udelay(300);	/* 300 uS is maximum time lock should take */
 
 	while (time_out) {
 		if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
 			time_out--;
-			udelay(1);
+			udelay(20);	/* Wait 20 uS more if needed */
 		} else
 			break;
 	}
 	if (!time_out) {
-		printf("PCIE: VCO output not locked\n");
+		printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
+			"PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
+
 		return -1;
 	}
 	return 0;
diff --git a/include/configs/intip.h b/include/configs/intip.h
index 4f7bc7e..19f12fa 100644
--- a/include/configs/intip.h
+++ b/include/configs/intip.h
@@ -172,7 +172,7 @@
 #define CONFIG_SYS_SDRAM_R3BAS		0x00000000
 #define CONFIG_SYS_SDRAM_PLBADDULL	0x00000000
 #define CONFIG_SYS_SDRAM_PLBADDUHB	0x00000008
-#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C80
+#define CONFIG_SYS_SDRAM_CONF1LL	0x80001C00
 #define CONFIG_SYS_SDRAM_CONF1HB	0x80001C80
 #define CONFIG_SYS_SDRAM_CONFPATHB	0x10a68000
 
@@ -181,7 +181,7 @@
 #define CONFIG_SYS_SDRAM0_MB1CF		0x00000000
 #define CONFIG_SYS_SDRAM0_MB2CF		0x00000000
 #define CONFIG_SYS_SDRAM0_MB3CF		0x00000000
-#define CONFIG_SYS_SDRAM0_MCOPT1	0x05122000
+#define CONFIG_SYS_SDRAM0_MCOPT1	0x05120000
 #define CONFIG_SYS_SDRAM0_MCOPT2	0x00000000
 #define CONFIG_SYS_SDRAM0_MODT0		0x00000000
 #define CONFIG_SYS_SDRAM0_MODT1		0x00000000
@@ -193,7 +193,7 @@
 #define CONFIG_SYS_SDRAM0_INITPLR1	0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR2	0x81020000
 #define CONFIG_SYS_SDRAM0_INITPLR3	0x81030000
-#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR4	0x81010002
 #define CONFIG_SYS_SDRAM0_INITPLR5	0xE4000542
 #define CONFIG_SYS_SDRAM0_INITPLR6	0x81900400
 #define CONFIG_SYS_SDRAM0_INITPLR7	0x8A880000
@@ -201,21 +201,21 @@
 #define CONFIG_SYS_SDRAM0_INITPLR9	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR10	0x8A880000
 #define CONFIG_SYS_SDRAM0_INITPLR11	0x81000442
-#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010380
-#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010000
+#define CONFIG_SYS_SDRAM0_INITPLR12	0x81010382
+#define CONFIG_SYS_SDRAM0_INITPLR13	0x81010002
 #define CONFIG_SYS_SDRAM0_INITPLR14	0x00000000
 #define CONFIG_SYS_SDRAM0_INITPLR15	0x00000000
 #define CONFIG_SYS_SDRAM0_RQDC		0x80000038
-#define CONFIG_SYS_SDRAM0_RFDC		0x003F0000
-#define CONFIG_SYS_SDRAM0_RDCC		0x80000000
+#define CONFIG_SYS_SDRAM0_RFDC		0x00000257
+#define CONFIG_SYS_SDRAM0_RDCC		0x40000000
 #define CONFIG_SYS_SDRAM0_DLCR		0x00000000
 #define CONFIG_SYS_SDRAM0_CLKTR		0x40000000
-#define CONFIG_SYS_SDRAM0_WRDTR		0x84000800
+#define CONFIG_SYS_SDRAM0_WRDTR		0x84000823
 #define CONFIG_SYS_SDRAM0_SDTR1		0x80201000
 #define CONFIG_SYS_SDRAM0_SDTR2		0x32204232
-#define CONFIG_SYS_SDRAM0_SDTR3		0x090B0D15
+#define CONFIG_SYS_SDRAM0_SDTR3		0x090C0D15
 #define CONFIG_SYS_SDRAM0_MMODE		0x00000442
-#define CONFIG_SYS_SDRAM0_MEMODE	0x00000000
+#define CONFIG_SYS_SDRAM0_MEMODE	0x00000002
 
 #define CONFIG_SYS_MBYTES_SDRAM	256	/* 256MB */