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authorYork Sun <yorksun@freescale.com>2012-02-29 12:36:51 +0000
committerAndy Fleming <afleming@freescale.com>2012-04-24 23:58:30 -0500
commit1ba62f10172ead798a8176435cfffff2f79f21c5 (patch)
tree5e9b575825060fae4ebefa3193ad5f1124c0fefd
parent119a55f9cff4884a0ad3353d8752ee8787e232da (diff)
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powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards
P1010RDB and p1_pc_rdb_pc has incorrect configuration for CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING. Incorrect setting causes DDR failure in case of SPD absent. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
-rw-r--r--board/freescale/p1010rdb/ddr.c6
-rw-r--r--board/freescale/p1_p2_rdb_pc/ddr.c4
-rw-r--r--include/configs/P1010RDB.h2
-rw-r--r--include/configs/p1_p2_rdb_pc.h2
4 files changed, 7 insertions, 7 deletions
diff --git a/board/freescale/p1010rdb/ddr.c b/board/freescale/p1010rdb/ddr.c
index e5d8423..36c8545 100644
--- a/board/freescale/p1010rdb/ddr.c
+++ b/board/freescale/p1010rdb/ddr.c
@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_DDR_RAW_TIMING
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
@@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void)
return ddr_size;
}
-#else /* CONFIG_DDR_RAW_TIMING */
+#else /* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
@@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts,
}
}
-#endif /* CONFIG_DDR_RAW_TIMING */
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c
index f0cbde7..88ba56f 100644
--- a/board/freescale/p1_p2_rdb_pc/ddr.c
+++ b/board/freescale/p1_p2_rdb_pc/ddr.c
@@ -15,7 +15,7 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
-#ifdef CONFIG_DDR_RAW_TIMING
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
defined(CONFIG_P1021RDB) || \
defined(CONFIG_P1020UTM)
@@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0;
}
-#endif /* CONFIG_DDR_RAW_TIMING */
+#endif /* CONFIG_SYS_DDR_RAW_TIMING */
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f2d3366..08fc4e8 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -181,7 +181,7 @@
/* DDR Setup */
#define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 3098c5a..a8db06f 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -227,7 +227,7 @@
/* DDR Setup */
#define CONFIG_FSL_DDR3
-#define CONFIG_DDR_RAW_TIMING
+#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52