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| author | Dave Liu <daveliu@freescale.com> | 2009-12-16 10:24:38 -0600 |
|---|---|---|
| committer | Kumar Gala <galak@kernel.crashing.org> | 2010-01-05 13:49:27 -0600 |
| commit | 1aa3d08a0244506b94031522e54fe06ee7a5ae0e (patch) | |
| tree | 3ee7b5c3cd7350ce189163f6d96a69c059e12c06 | |
| parent | bdc9f7b5eab8d5edd8a8cc5d80ef080836b00e85 (diff) | |
| download | u-boot-imx-1aa3d08a0244506b94031522e54fe06ee7a5ae0e.zip u-boot-imx-1aa3d08a0244506b94031522e54fe06ee7a5ae0e.tar.gz u-boot-imx-1aa3d08a0244506b94031522e54fe06ee7a5ae0e.tar.bz2 | |
fsl-ddr: add override for the Rtt_Wr
Different boards may require different settings of Dynamic ODT (Rtt_Wr).
We provide a means to allow the board specific code to provide its own
value of Rtt_Wr.
Signed-off-by: Dave Liu <daveliu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| -rw-r--r-- | cpu/mpc8xxx/ddr/ctrl_regs.c | 10 | ||||
| -rw-r--r-- | include/asm-ppc/fsl_ddr_sdram.h | 1 |
2 files changed, 8 insertions, 3 deletions
diff --git a/cpu/mpc8xxx/ddr/ctrl_regs.c b/cpu/mpc8xxx/ddr/ctrl_regs.c index 5e37ca6..3be7e22 100644 --- a/cpu/mpc8xxx/ddr/ctrl_regs.c +++ b/cpu/mpc8xxx/ddr/ctrl_regs.c @@ -576,18 +576,22 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr, } /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */ -static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr) +static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr, + const memctl_options_t *popts) { unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */ unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */ #if defined(CONFIG_FSL_DDR3) - unsigned int rtt_wr = 2; /* 120 ohm Rtt_WR */ + unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */ unsigned int srt = 0; /* self-refresh temerature, normal range */ unsigned int asr = 0; /* auto self-refresh disable */ unsigned int cwl = compute_cas_write_latency() - 5; unsigned int pasr = 0; /* partial array self refresh disable */ + if (popts->rtt_override) + rtt_wr = popts->rtt_wr_override_value; + esdmode2 = (0 | ((rtt_wr & 0x3) << 9) | ((srt & 0x1) << 7) @@ -1330,7 +1334,7 @@ compute_fsl_memctl_config_regs(const memctl_options_t *popts, set_ddr_sdram_cfg_2(ddr, popts); set_ddr_sdram_mode(ddr, popts, common_dimm, cas_latency, additive_latency); - set_ddr_sdram_mode_2(ddr); + set_ddr_sdram_mode_2(ddr, popts); set_ddr_sdram_interval(ddr, popts, common_dimm); set_ddr_data_init(ddr); set_ddr_sdram_clk_cntl(ddr, popts); diff --git a/include/asm-ppc/fsl_ddr_sdram.h b/include/asm-ppc/fsl_ddr_sdram.h index 15ab675..3216a50 100644 --- a/include/asm-ppc/fsl_ddr_sdram.h +++ b/include/asm-ppc/fsl_ddr_sdram.h @@ -192,6 +192,7 @@ typedef struct memctl_options_s { /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ + unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ /* Automatic self refresh */ unsigned int auto_self_refresh_en; |