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authorStephen Warren <swarren@nvidia.com>2016-07-27 15:24:51 -0600
committerTom Warren <twarren@nvidia.com>2016-08-04 13:36:59 -0700
commit19014203c4b54c499fc490c7d4c53c5aea7704c5 (patch)
tree01159931fe56764ef87a23617b826b201c25d537
parent6e7a11e64e7a97b309e792af5410d47976b6ecec (diff)
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ARM: tegra: add BPMP and dependencies to Tegra186 DT
This adds the DT content that's needed to allow board DTs to enable use of BPMP, clocks, resets, GPIOs, eMMC, and SD cards. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
-rw-r--r--arch/arm/dts/tegra186.dtsi55
1 files changed, 53 insertions, 2 deletions
diff --git a/arch/arm/dts/tegra186.dtsi b/arch/arm/dts/tegra186.dtsi
index 650feb6..25e1e8d 100644
--- a/arch/arm/dts/tegra186.dtsi
+++ b/arch/arm/dts/tegra186.dtsi
@@ -1,14 +1,16 @@
#include "skeleton.dtsi"
+#include <dt-bindings/clock/tegra186-clock.h>
#include <dt-bindings/gpio/tegra186-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/tegra186-hsp.h>
+#include <dt-bindings/reset/tegra186-reset.h>
/ {
compatible = "nvidia,tegra186";
#address-cells = <2>;
#size-cells = <2>;
- gpio@2200000 {
+ gpio_main: gpio@2200000 {
compatible = "nvidia,tegra186-gpio";
reg-names = "security", "gpio";
reg =
@@ -34,9 +36,24 @@
status = "disabled";
};
+ sdhci@3400000 {
+ compatible = "nvidia,tegra186-sdhci";
+ reg = <0x0 0x03400000 0x0 0x200>;
+ resets = <&bpmp TEGRA186_RESET_SDMMC1>;
+ reset-names = "sdmmc";
+ clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
+ clock-names = "sdmmc";
+ interrupts = <GIC_SPI 62 0x04>;
+ status = "disabled";
+ };
+
sdhci@3460000 {
compatible = "nvidia,tegra186-sdhci";
reg = <0x0 0x03460000 0x0 0x200>;
+ resets = <&bpmp TEGRA186_RESET_SDMMC4>;
+ reset-names = "sdmmc";
+ clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
+ clock-names = "sdmmc";
interrupts = <GIC_SPI 31 0x04>;
status = "disabled";
};
@@ -49,7 +66,7 @@
#mbox-cells = <2>;
};
- gpio@c2f0000 {
+ gpio_aon: gpio@c2f0000 {
compatible = "nvidia,tegra186-gpio-aon";
reg-names = "security", "gpio";
reg =
@@ -62,4 +79,38 @@
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ sysram@30000000 {
+ compatible = "nvidia,tegra186-sysram", "mmio-sram";
+ reg = <0x0 0x30000000 0x0 0x50000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>;
+
+ sysram_cpu_bpmp_tx: shmem@4e000 {
+ compatible = "nvidia,tegra186-bpmp-shmem";
+ reg = <0x0 0x4e000 0x0 0x1000>;
+ };
+
+ sysram_cpu_bpmp_rx: shmem@4f000 {
+ compatible = "nvidia,tegra186-bpmp-shmem";
+ reg = <0x0 0x4f000 0x0 0x1000>;
+ };
+ };
+
+ bpmp: bpmp {
+ compatible = "nvidia,tegra186-bpmp";
+ mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>;
+ /*
+ * In theory, these references, and the configuration in the
+ * node these reference point at, are board-specific, since
+ * they depend on the BCT's memory carve-out setup, the
+ * firmware that's actually loaded onto the BPMP, etc. However,
+ * in practice, all boards are likely to use identical values.
+ */
+ shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
};