MLK-14484-3 mx7ulp_arm2: Convert to use OF_CONTROL

Add the 10x10 ARM2 and 14x14 ARM2 DTS files. Also convert the board
codes to use OF_CONTROL and DM drivers.

Since the DTS files only have UART and SD1 supported. So we only enable
the DM for these two modules. QSPI and USB are still kept in non-DM fashion.

Signed-off-by: Ye Li <ye.li@nxp.com>

7 files changed, 183 insertions, 58 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3569078..68c06de 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -376,7 +376,9 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
 		imx7d-19x19-lpddr3-arm2.dtb
 
 dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \
-		imx7ulp-evk-qspi.dtb
+		imx7ulp-evk-qspi.dtb \
+		imx7ulp-10x10-arm2.dtb \
+		imx7ulp-14x14-arm2.dtb
 
 dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \
 	keystone-k2l-evm.dtb \
diff --git a/arch/arm/dts/imx7ulp-10x10-arm2.dts b/arch/arm/dts/imx7ulp-10x10-arm2.dts
new file mode 100644
index 0000000..c3e19e1
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-10x10-arm2.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP 10x10 arm2";
+	compatible = "fsl,imx7ulp-10x10-arm2", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x40A60000,115200";
+		stdout-path = &lpuart6;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+
+	imx7ulp-10x10-arm2 {
+		pinctrl_lpuart6: lpuart6grp {
+			fsl,pins = <
+				ULP1_PAD_PTE11__LPUART6_RX	0x400
+				ULP1_PAD_PTE10__LPUART6_TX	0x400
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				ULP1_PAD_PTE3__SDHC1_CMD	0x843
+				ULP1_PAD_PTE2__SDHC1_CLK	0x843
+				ULP1_PAD_PTE4__SDHC1_D3		0x843
+				ULP1_PAD_PTE5__SDHC1_D2		0x843
+				ULP1_PAD_PTE0__SDHC1_D1		0x843
+				ULP1_PAD_PTE1__SDHC1_D0		0x843
+			>;
+		};
+	};
+};
+
+&lpuart6 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart6>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
diff --git a/arch/arm/dts/imx7ulp-14x14-arm2.dts b/arch/arm/dts/imx7ulp-14x14-arm2.dts
new file mode 100644
index 0000000..defa097
--- /dev/null
+++ b/arch/arm/dts/imx7ulp-14x14-arm2.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx7ulp.dtsi"
+
+/ {
+	model = "NXP i.MX7ULP 14x14 arm2";
+	compatible = "fsl,imx7ulp-14x14-arm2", "fsl,imx7ulp", "Generic DT based system";
+
+	chosen {
+		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
+		stdout-path = &lpuart4;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x60000000 0x40000000>;
+	};
+};
+
+&iomuxc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog_1>;
+
+	imx7ulp-14x14-arm2 {
+		pinctrl_hog_1: hoggrp-1 {
+			fsl,pins = <
+				ULP1_PAD_PTC10__PTC10		0x30100
+				ULP1_PAD_PTC1__PTC1		0x20100
+			>;
+		};
+
+		pinctrl_lpuart4: lpuart4grp {
+			fsl,pins = <
+				ULP1_PAD_PTC3__LPUART4_RX	0x400
+				ULP1_PAD_PTC2__LPUART4_TX	0x400
+			>;
+		};
+
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				ULP1_PAD_PTE3__SDHC1_CMD	0x843
+				ULP1_PAD_PTE2__SDHC1_CLK	0x843
+				ULP1_PAD_PTE4__SDHC1_D3		0x843
+				ULP1_PAD_PTE5__SDHC1_D2		0x843
+				ULP1_PAD_PTE0__SDHC1_D1		0x843
+				ULP1_PAD_PTE1__SDHC1_D0		0x843
+			>;
+		};
+	};
+};
+
+&lpuart4 { /* console */
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart4>;
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1>;
+	non-removable;
+	status = "okay";
+};
diff --git a/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
index 84a5f11..ba945e5 100644
--- a/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
+++ b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
@@ -40,18 +40,6 @@ int dram_init(void)
 	return 0;
 }
 
-static int mx7ulp_board_rev(void)
-{
-	return 0x41;
-}
-
-u32 get_board_rev(void)
-{
-	int rev = mx7ulp_board_rev();
-
-	return (get_cpu_rev() & ~(0xF << 8)) | rev;
-}
-
 static iomux_cfg_t const lpuart4_pads[] = {
     MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
     MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -214,7 +202,7 @@ int board_init(void)
 	return 0;
 }
 
-#ifdef CONFIG_FSL_ESDHC
+#ifndef CONFIG_DM_MMC
 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
 	{USDHC0_RBASE, 0, 8},
 	{USDHC1_RBASE, 0},
diff --git a/configs/mx7ulp_10x10_arm2_defconfig b/configs/mx7ulp_10x10_arm2_defconfig
index e0875b2..4273ca0 100644
--- a/configs/mx7ulp_10x10_arm2_defconfig
+++ b/configs/mx7ulp_10x10_arm2_defconfig
@@ -2,9 +2,27 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage_lpddr2
 CONFIG_ARM=y
 CONFIG_ARCH_MX7ULP=y
 CONFIG_TARGET_MX7ULP_10X10_ARM2=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-10x10-arm2"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-10x10-arm2.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
 CONFIG_DM=y
-CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_IMX_RGPIO2P=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+# CONFIG_BLK is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_ULP_WATCHDOG=y
diff --git a/configs/mx7ulp_14x14_arm2_defconfig b/configs/mx7ulp_14x14_arm2_defconfig
index 25eb39d..62f4dca 100644
--- a/configs/mx7ulp_14x14_arm2_defconfig
+++ b/configs/mx7ulp_14x14_arm2_defconfig
@@ -2,9 +2,27 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage.cfg"
 CONFIG_ARM=y
 CONFIG_ARCH_MX7ULP=y
 CONFIG_TARGET_MX7ULP_14X14_ARM2=y
-CONFIG_SYS_MALLOC_F=y
-CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-14x14-arm2"
+CONFIG_DEFAULT_FDT_FILE="imx7ulp-14x14-arm2.dtb"
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_OF_CONTROL=y
 CONFIG_DM=y
-CONFIG_DM_SERIAL=y
 CONFIG_DM_GPIO=y
 CONFIG_IMX_RGPIO2P=y
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX7ULP=y
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+# CONFIG_DM_MMC_OPS is not set
+# CONFIG_BLK is not set
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CMD_GPIO=y
+CONFIG_ULP_WATCHDOG=y
diff --git a/include/configs/mx7ulp_arm2.h b/include/configs/mx7ulp_arm2.h
index d3d601b..cfdf418 100644
--- a/include/configs/mx7ulp_arm2.h
+++ b/include/configs/mx7ulp_arm2.h
@@ -12,9 +12,6 @@
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
-/*Uncomment it to use plugin boot*/
-/*#define CONFIG_USE_PLUGIN*/
-
 /*Uncomment it to use secure boot*/
 /*#define CONFIG_SECURE_BOOT*/
 
@@ -24,10 +21,8 @@
 #endif
 #endif
 
-#define CONFIG_SYS_VSNPRINTF
 #define CONFIG_BOARD_POSTCLK_INIT
-#define CONFIG_IMX_FIXED_IVT_OFFSET
-#define CONFIG_SYS_BOOTM_LEN   0x1000000
+#define CONFIG_SYS_BOOTM_LEN		0x1000000
 
 #define SRC_BASE_ADDR           CMC1_RBASE
 #define IRAM_BASE_ADDR          OCRAM_0_BASE
@@ -37,10 +32,6 @@
 #define CONFIG_CMD_FUSE
 #define CONFIG_MXC_OCOTP
 
-/* MMC Configs */
-#define CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_GENERIC_MMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
@@ -63,21 +54,11 @@
 
 /* Using ULP WDOG for reset */
 #define WDOG_BASE_ADDR		 WDG1_RBASE
-#define CONFIG_ULP_WATCHDOG
 
 
 #define CONFIG_SYS_ARCH_TIMER
 #define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
 
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-
-/* uncomment for PLUGIN mode support */
-/* #define CONFIG_USE_PLUGIN */
-
-/* uncomment for SECURE mode support */
-/* #define CONFIG_SECURE_BOOT */
-
 #define CONFIG_INITRD_TAG
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -86,13 +67,7 @@
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
 
-#define CONFIG_BOARD_LATE_INIT
-#define CONFIG_BOARD_EARLY_INIT_F
-
 /* UART */
-#define CONFIG_FSL_LPUART
-#define CONFIG_LPUART_32LE_REG
-
 #ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
 #define LPUART_BASE     LPUART6_RBASE
 #else
@@ -104,13 +79,10 @@
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
 
-
 #undef CONFIG_CMD_IMLS
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_SYS_HUSH_PARSER
 
-#define CONFIG_BOOTDELAY		1
 #define CONFIG_SYS_CACHELINE_SIZE      64
 
 /* Miscellaneous configurable options */
@@ -140,7 +112,6 @@
 #define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_OF_LIBFDT
 
 #define CONFIG_LOADADDR             0x60800000
 
@@ -152,8 +123,6 @@
 #define CONFIG_DEFAULT_FDT_FILE		"imx7ulp-14x14-arm2.dtb"
 #endif
 
-#define CONFIG_MFG_NAND_PARTITION
-
 #define CONFIG_MFG_ENV_SETTINGS \
 	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
 		"rdinit=/linuxrc " \
@@ -161,7 +130,6 @@
 		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
 		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
 		"g_mass_storage.iSerialNumber=\"\" "\
-		CONFIG_MFG_NAND_PARTITION \
 		"\0" \
 		"initrd_addr=0x63800000\0" \
 		"initrd_high=0xffffffff\0" \
@@ -231,9 +199,6 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-
 #ifndef CONFIG_SYS_DCACHE_OFF
 #define CONFIG_CMD_CACHE
 #endif
@@ -271,8 +236,6 @@
 #endif
 #define QSPI0_BASE_ADDR                 0x410A5000
 #define QSPI0_AMBA_BASE                 0xC0000000
-#define CONFIG_QSPI_BASE	QSPI0_BASE_ADDR
-#define CONFIG_QSPI_MEMMAP_BASE	QSPI0_AMBA_BASE
 #endif
 
 #endif	/* __CONFIG_H */