IGEP0146: Add Support for Peripherials

SD
I2C
eMMC
Tuned DRAM
E²PROM
Ethernet Fix using Hysteresis in MUX along with other pad control options

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

12 files changed, 841 insertions, 528 deletions

diff --git a/board/isee/igep0046/Kconfig b/board/isee/igep0046/Kconfig
index c932c91..0e6820e 100644
--- a/board/isee/igep0046/Kconfig
+++ b/board/isee/igep0046/Kconfig
@@ -9,17 +9,8 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "igep0046"
 
-choice
-	prompt "Carrier Board"
-	default BASE0040
-	optional
-
 config BASE0040
-	bool "Carrier board base0040"
-	help
-	  This is the igep base0040 carrier board.
-
-endchoice
+	bool "base0040"
 
 config WITH_SPL_SUPPORT
 	bool "Build i.MX6 with SPL support"
diff --git a/board/isee/igep0146/Kconfig b/board/isee/igep0146/Kconfig
index 69496fd..661f355 100644
--- a/board/isee/igep0146/Kconfig
+++ b/board/isee/igep0146/Kconfig
@@ -9,4 +9,6 @@ config SYS_VENDOR
 config SYS_CONFIG_NAME
 	default "igep0146"
 
+config BASE0040
+	bool "base0040"
 endif
diff --git a/board/isee/igep0146/MAINTAINERS b/board/isee/igep0146/MAINTAINERS
index 4f06e15..4ba667e 100644
--- a/board/isee/igep0146/MAINTAINERS
+++ b/board/isee/igep0146/MAINTAINERS
@@ -1,6 +1,7 @@
-IGEP0046 BOARD
+IGEP0146 BOARD
 M:	Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
 S:	Maintained
 F:	board/isee/igep0146/igep0146.c
 F:	include/configs/igep0146.h
+F:	board/isee/igep0146/mx6ul_igep0146_1x512.cfg
 F:	configs/mx6ul_igep0146_512M_defconfig
diff --git a/board/isee/igep0146/Makefile b/board/isee/igep0146/Makefile
index 7cab156..f8f19af 100644
--- a/board/isee/igep0146/Makefile
+++ b/board/isee/igep0146/Makefile
@@ -6,4 +6,5 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
+obj-y  += igep0146_eeprom.o
 obj-y  += igep0146.o
diff --git a/board/isee/igep0146/igep0146.c b/board/isee/igep0146/igep0146.c
index da7a348..35c5432 100644
--- a/board/isee/igep0146/igep0146.c
+++ b/board/isee/igep0146/igep0146.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
  *
- * Source file for IGEP0046 board
+ * Source file for IGEP0146 board
  *
  * Author: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>
  *
@@ -26,6 +26,19 @@
 #include <asm/io.h>
 #include "../common/igep_common.h"
 
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+/*
+#include <usb.h>
+#include <usb/ehci-ci.h>
+*/
+
+#include <netdev.h>
+#include <miiphy.h>
+#include <i2c.h>
+#include "igep0146_eeprom.h"
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* MACRO MUX defines */
@@ -38,6 +51,35 @@ DECLARE_GLOBAL_DATA_PTR;
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm |	\
 	PAD_CTL_SRE_FAST )
 
+#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_SPEED_HIGH   |                                   \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_TR_CTRL  ( PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | PAD_CTL_SPEED_HIGH  | \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_CLK_PAD_CTRL  (PAD_CTL_DSE_DISABLE | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define MDIO_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |     \
+	PAD_CTL_DSE_48ohm   | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_22K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#ifdef CONFIG_SYS_I2C_MXC
+#define I2C_PAD_CTRL  ( PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+#endif
+
+/* Audio reset */
+#define AUDIO_RESET	IMX_GPIO_NR(4, 17)
+/* Ethernet Phy 1 reset */
+#define ETH_PHY_RESET	IMX_GPIO_NR(1, 10)
+/* eMMC reset */
+#define USDHC2_PWR_GPIO	IMX_GPIO_NR(4, 10)
+
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
@@ -50,7 +92,7 @@ void dram_init_banksize(void)
 	gd->bd->bi_dram[0].size = imx_ddr_size();
 }
 
-/* UART MUX */
+/* uart */
 static iomux_v3_cfg_t const uart3_pads[] =
 {
 	MX6_PAD_UART3_TX_DATA__UART3_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -59,9 +101,114 @@ static iomux_v3_cfg_t const uart3_pads[] =
 
 static iomux_v3_cfg_t const led_pads[] = {
 	MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
+	/* Warning This GPIO actually controls if we select SD or WiFi through a MUX */
 	MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(GPIO_LED_PAD_CTRL),
+
+};
+
+#ifdef CONFIG_FEC_MXC
+/* ethernet */
+static iomux_v3_cfg_t const enet1_pads[] = {
+	
+	MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
+	MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
+	
+	MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_TR_CTRL),
+	MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_TR_CTRL),
+
+	MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_TR_CTRL),
+	MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_TR_CTRL),
+
+	MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
+
+	/* ethernet reset */
+	MX6_PAD_JTAG_MOD__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+
+};
+#endif
+
+/* sd 1 */
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+};
+
+/* emmc */
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+	MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+	/* emmc Reset */
+	MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+/* gpio misc */
+static iomux_v3_cfg_t const init_pads[] =
+{
+	/* TLV320AIC3106 Audio codec Reset*/
+	MX6_PAD_CSI_MCLK__GPIO4_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+const uchar igep_mac0 [6] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0xff };
+//const uchar igep_mac0 [6] = { 0xb0, 0xd5, 0xcc, 0xb2, 0xa5, 0xb9 };
+
+static int igep_eeprom_valid = 0;
+static struct igep_mf_setup igep0046_eeprom_config;
+
+/* i2c */
+#ifdef CONFIG_SYS_I2C_MXC
+static struct i2c_pads_info i2c_pad_info1 =
+{
+	.scl =
+	{
+		.i2c_mode = MX6_PAD_UART4_TX_DATA__I2C1_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 28)
+	},
+	.sda =
+	{
+		.i2c_mode = MX6_PAD_UART4_RX_DATA__I2C1_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_UART4_RX_DATA__GPIO1_IO29 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 29)
+	}
 };
 
+static struct i2c_pads_info i2c_pad_info2 =
+{
+	.scl =
+	{
+		.i2c_mode = MX6_PAD_UART5_TX_DATA__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_UART5_TX_DATA__GPIO1_IO30 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 30)
+	},
+	.sda =
+	{
+		.i2c_mode = MX6_PAD_UART5_RX_DATA__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_UART5_RX_DATA__GPIO1_IO31 | I2C_PAD,
+		.gp = IMX_GPIO_NR(1, 31)
+	}
+};
+#endif
+
 
 static void setup_iomux_uart(void)
 {
@@ -73,6 +220,161 @@ static void setup_iomux_leds(void)
 	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
 }
 
+/*
+static void setup_iomux_usdhc(void)
+{
+	imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+
+}
+*/
+
+static void setup_iomux_enet(void)
+{
+	imx_iomux_v3_setup_multiple_pads(enet1_pads, ARRAY_SIZE(enet1_pads));
+}
+
+static void setup_iomux_misc(void)
+{
+	imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
+}
+
+
+const uchar* get_mac_address (void)
+{
+	if(igep_eeprom_valid)
+		return igep0046_eeprom_config.bmac0;
+	return igep_mac0;
+}
+
+#ifdef CONFIG_BASE0040
+static void reset_audio(void)
+{
+	/* Audio Reset */
+	gpio_direction_output(AUDIO_RESET, 0);
+	mdelay(5);
+}
+#endif
+
+#ifdef CONFIG_FEC_MXC
+
+#ifdef CONFIG_RESET_PHY_R
+void reset_phy(void)
+{
+}
+#endif /* CONFIG_RESET_PHY_R */
+
+void mu_reset_phy(void)
+{
+	/* Reset LAN8720 PHY */
+	gpio_request(ETH_PHY_RESET, "LAN8720 PHY RST");
+	gpio_direction_output(ETH_PHY_RESET , 0);
+	mdelay(2);
+	gpio_set_value(ETH_PHY_RESET, 1);
+	mdelay(2);
+
+}
+
+static int setup_phy(void)
+{
+	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* clear gpr1[17], set gpr1[13] to select external anatop clock for ENET1 (actually provided by PHY) */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK, IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
+
+	/* clear gpr1[17], set gpr1[14] to select external anatop clock for ENET2 (actually provided by PHY) */
+	clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK, IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK);
+	
+	//enable_fec_anatop_clock(0, ENET_50MHZ);
+	//enable_enet_clk(1);
+
+	return 0;
+
+}
+
+int board_eth_init(bd_t *bis)
+{
+
+	int ret = 0 ;
+	eth_setenv_enetaddr("ethaddr", get_mac_address());
+	setup_iomux_enet();
+	setup_phy();
+	mu_reset_phy();
+
+	ret = fecmxc_initialize_multi(bis, 0, CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
+	if (ret)
+		printf("FEC%d MXC: %s:failed\n", 0, __func__);
+
+	return 0;
+}
+
+#endif
+
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 4},
+	{USDHC2_BASE_ADDR, 0, 8},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+
+	/* we will consider at the moment that SD1 / eMMC are always present */
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		/* SD case */
+		ret = 1;
+		/* WiFi case */
+		break;
+	case USDHC2_BASE_ADDR:
+		/* eMMC case */
+		/* Nand case */
+		/* QPSI case */
+		/* SD2 case */
+		ret = 1;
+		break;
+	}
+
+	return ret;
+
+}
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-boot device node)    (Physical Port)
+	 * mmc0                    USDHC1	--> SD1 / Wifi
+	 * mmc1                    USDHC2	--> eMMC / NAND / QSPI / SD2
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ 			/* USDHC1 Clock */
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+			break;
+		case 1:
+			imx_iomux_v3_setup_multiple_pads(
+				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
+ 			/* USDHC2 Clock */
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+			break;
+		}	
+		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+		if (ret) {
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+		}
+	}
+	return 0;
+}
+
+
 
 int checkboard(void)
 {
@@ -83,17 +385,44 @@ int board_early_init_f(void)
 {
 	setup_iomux_uart();
 	setup_iomux_leds();
-	
-	/* configure LEDS */
-	gpio_direction_output(IMX_GPIO_NR(1, 8), 1);
-	gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
-
+	setup_iomux_misc();
 	return 0;
 }
 
 int board_init(void)
 {
 
+	u32 crc_value = 0;
+   	u32 crc_save_value = 0;
+
+#ifdef CONFIG_BASE0040
+	reset_audio();
+#endif
+
+#ifdef CONFIG_SYS_I2C_MXC
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	mdelay(1);
+#endif
+
+  if(check_eeprom() != 0){
+	printf("EEPROM: not found\n");
+    }else{
+		/* Read configuration from eeprom */
+		if(eeprom46_read_setup(0, (char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup)))
+	  	printf("EEPROM: read fail\n");	
+		/* Verify crc32 */
+	   	crc_save_value = igep0046_eeprom_config.crc32;
+    	igep0046_eeprom_config.crc32 = 0;
+	   	crc_value = crc32(0, (const unsigned char*) &igep0046_eeprom_config, sizeof(struct igep_mf_setup));
+		if(crc_save_value != crc_value){
+       	printf("EEPROM: CRC32 failed. Loading default MAC\n");				
+		}else{
+	    printf("EEPROM: CRC32 OK! Loading MAC from eeprom\n");	       		
+	  	igep_eeprom_valid = 1;
+		}
+	}
+
 	return 0;	
 }
 
@@ -101,7 +430,6 @@ int board_init(void)
 int board_late_init(void)
 {	
 	checkboard();
-	puts("\n");
 	return 0;
 }
 
@@ -111,4 +439,70 @@ void ldo_mode_set(int ldo_bypass)
 {
 	return;
 }
-#endif
\ No newline at end of file
+#endif
+
+/* Configure for SPL BUILD */
+
+#ifdef CONFIG_SPL_BUILD
+#include <libfdt.h>
+#include <spl.h>
+#include <asm/arch/mx6-ddr.h>
+
+/* ENTIRE RAM CALIBRATION STRUCTURES MISSING */
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0xFFFFFFFF, &ccm->CCGR0);
+	writel(0xFFFFFFFF, &ccm->CCGR1);
+	writel(0xFFFFFFFF, &ccm->CCGR2);
+	writel(0xFFFFFFFF, &ccm->CCGR3);
+	writel(0xFFFFFFFF, &ccm->CCGR4);
+	writel(0xFFFFFFFF, &ccm->CCGR5);
+	writel(0xFFFFFFFF, &ccm->CCGR6);
+	writel(0xFFFFFFFF, &ccm->CCGR7);
+}
+
+static void spl_dram_init(void)
+{
+	/* COMMENTED UNTIL VALID RAM CONFIGURATION FOUND */ 
+	/*
+	mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
+	mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
+	*/
+}
+
+/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
+/* its our chance to print info about boot device */
+void spl_board_init(void)
+{
+	
+}
+
+void board_init_f(ulong dummy)
+{
+	ccgr_init();
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* iomux of uart and leds */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+	
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+#endif
diff --git a/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg b/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg
deleted file mode 100644
index e36084c..0000000
--- a/board/isee/igep0146/mx6ul_igep0146_1x128_nt.cfg
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-
-BOOT_FROM	sd
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-
-/* New DDR type MT41K64M16TW-107 */
-
-//=============================================================================			
-// Enable all clocks (they are disabled by ROM code)			
-//=============================================================================	
-
-DATA 4 0x020c4068 0xffffffff    // CCM_CCGR0
-DATA 4 0x020c406c 0xffffffff    // CCM_CCGR1
-DATA 4 0x020c4070 0xffffffff    // CCM_CCGR2
-DATA 4 0x020c4074 0xffffffff    // CCM_CCGR3
-DATA 4 0x020c4078 0xffffffff    // CCM_CCGR4
-DATA 4 0x020c407c 0xffffffff    // CCM_CCGR5
-DATA 4 0x020c4080 0xffffffff    // CCM_CCGR6
-
-//=============================================================================			
-// IOMUX IMX6UL - MCIMX6G3CV
-//=============================================================================
-
-//DDR IO TYPE:				
-DATA 4 0x020E04B4 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
-DATA 4 0x020E04AC 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
-
-//CLOCK:			
-DATA 4 0x020E027C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
-
-//ADDRESS:
-DATA 4 0x020E0250 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B			
-DATA 4 0x020E024C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
-DATA 4 0x020E0490 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS
-
-//Control:
-DATA 4 0x020E0288 0x000C0030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET			
-DATA 4 0x020E0270 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
-DATA 4 0x020E0260 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
-DATA 4 0x020E0264 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
-DATA 4 0x020E04A0 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS
-
-//Data Strobes:
-DATA 4 0x020E0494 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL			
-DATA 4 0x020E0280 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
-DATA 4 0x020E0284 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
-
-//Data:
-DATA 4 0x020E04B0 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
-DATA 4 0x020E0498 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS
-DATA 4 0x020E04A4 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS
-
-DATA 4 0x020E0244 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
-DATA 4 0x020E0248 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
-
-//=============================================================================			
-// DDR Controller Registers			
-//=============================================================================			
-// Manufacturer:	Micron		
-// Device Part Number:  MT41K64M16TW-107		
-// Clock Freq.: 933 MHz	IMX6UL ensures data capture margin up to 400 Mhz	
-// Density per CS in Gb: 1 Gb		
-// Chip Selects used:	1		
-// Number of Banks:	8		
-// Row address:    	13		
-// Column address: 	10		
-// Data bus width	16		
-//=============================================================================
-
-DATA 4 0x021B001C 0x00008000    // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
-			
-//=============================================================================			
-// Calibration setup.	REVISAR		
-//=============================================================================	
-
-DATA 4 0x021B0800 0xA1390003	// MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
-
-// For target board, may need to run write leveling calibration to fine tune these settings.			
-DATA 4 0x021B080C 0x00000000	// MMDC_MPWLDECTRL0
-
-// Read DQS Gating calibration
-DATA 4 0x021B083C 0x415C015C	// MMDC_MPDGCTRL0
-
-// Read Calibration
-DATA 4 0x021B0848 0x40404040	// MMDC_MPRDDLCTL 0x40404244
-
-// Write Calibration
-DATA 4 0x021B0850 0x40404040	// MMDC_MPWRDLCTL 0x40405A58
-
-// Read Data bit delay
-DATA 4 0x021B081C 0x33333333	// MMDC_MPRDDQBY0DL
-DATA 4 0x021B0820 0x33333333	// MMDC_MPRDDQBY1DL
-DATA 4 0x021B082C 0xf3333333	// MMDC_MPWRDQBY0DL
-DATA 4 0x021B0830 0xf3333333	// MMDC_MPWRDQBY1DL
-
-// Control Duty Cicle DQS of and primary clock CK0
-DATA 4 0x021B08C0 0x24922492	// MMDC_MPDCCR 0x00921012 24922492 0x00921012
-
-// Complete Calibration by Forced Measurement
-DATA 4 0x021B08b8 0x00008000    // MMDC_MPMUR0
-
-//=============================================================================			
-// Calibration setup end			
-//=============================================================================	
-
-// MMCD Init
-DATA 4 0x021B0004 0x00020036	// MMDC_MDPDC 
-DATA 4 0x021B0008 0x1B333030	// MMDC_MDOTC 
-DATA 4 0x021B000C 0x676B52F3	// MMDC_MDCFG0 
-DATA 4 0x021B0010 0xB66D0B63    // MMDC_MDCFG1
-DATA 4 0x021B0014 0x01FF00DB	// MMDC_MDCFG2
-
-//MDMISC: RALAT kept to the high level of 5. 			
-//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			
-//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			
-//b. Small performence improvment 
-DATA 4 0x021B0018 0x00201740	// MMDC_MDMISC
-DATA 4 0x021B001C 0x00000800    // MMDC_MDSCR
-DATA 4 0x021B002C 0x000026D2	// MMDC_MDRWD
-DATA 4 0x021B0030 0x006B1023	// MMDC_MDOR
-DATA 4 0x021B0040 0x0000004F	// MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
-DATA 4 0x021B0000 0x82180000	// MMDC_MDCTL
-
-// ????
-DATA 4 0x021B0890 0x00400000	// MMDC_MPPDCMPR2 DDR2 Only ???
-
-// Mode Register writes
-// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
-DATA 4 0x021B001C 0x02008032    // MMDC0_MDSCR, MR2 write, CS0
-DATA 4 0x021B001C 0x00008033	// MMDC0_MDSCR, MR3 write, CS0
-DATA 4 0x021B001C 0x00048031	// MMDC0_MDSCR, MR1 write, CS0
-DATA 4 0x021B001C 0x15208030	// MMDC0_MDSCR, MR0write, CS0
-DATA 4 0x021B001C 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
-
-
-DATA 4 0x021B0020 0x00000800    // MMDC0_MDREF
-
-DATA 4 0x021B0818 0x00000227	// DDR_PHY_P0_MPODTCTRL
-
-DATA 4 0x021B0004 0x0002552D	// MMDC0_MDPDC
-
-DATA 4 0x021B0404 0x00011006	// MMDC0_MAPSR
-
-DATA 4 0x021B001C 0x00000000	// MMDC0_MDSCR
diff --git a/board/isee/igep0146/mx6ul_igep0146_1x512.cfg b/board/isee/igep0146/mx6ul_igep0146_1x512.cfg
new file mode 100644
index 0000000..fc3b76c
--- /dev/null
+++ b/board/isee/igep0146/mx6ul_igep0146_1x512.cfg
@@ -0,0 +1,203 @@
+/*

+ * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz

+ *

+ * SPDX-License-Identifier:	GPL-2.0+

+ *

+ * Refer docs/README.imxmage for more details about how-to configure

+ * and create imximage boot image

+ *

+ * The syntax is taken as close as possible with the kwbimage

+ */

+

+/* image version */

+

+IMAGE_VERSION 2

+

+/*

+ * Boot Device : one of

+ * spi, sd (the board has no nand neither onenand)

+ */

+

+BOOT_FROM	sd

+

+#ifdef CONFIG_SECURE_BOOT

+CSF CONFIG_CSF_SIZE

+#endif

+

+/*

+ * Device Configuration Data (DCD)

+ *

+ * Each entry must have the format:

+ * Addr-type           Address        Value

+ *

+ * where:

+ *	Addr-type register length (1,2 or 4 bytes)

+ *	Address	  absolute address of the register

+ *	value	  value to be stored in the register

+ */

+

+/* DDR type MT41K256M16TW-107 */

+			

+//=============================================================================			

+// Enable all clocks (they are disabled by ROM code)			

+//=============================================================================			

+DATA 4	0x020c4068 0xffffffff	

+DATA 4	0x020c406c 0xffffffff	

+DATA 4	0x020c4070 0xffffffff	

+DATA 4	0x020c4074 0xffffffff	

+DATA 4	0x020c4078 0xffffffff	

+DATA 4	0x020c407c 0xffffffff	

+DATA 4	0x020c4080 0xffffffff	

+			

+			

+//=============================================================================			

+// IOMUX			

+//=============================================================================			

+//DDR IO TYPE:			

+DATA 4	0x020e04b4 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE -- tipo DDR3 (0x000C0000)

+DATA 4	0x020e04ac 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE   -- Pull keeper enable / disbale (enable = 0x00001000)

+			

+//CLOCK:			

+DATA 4	0x020e027c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0	-- (R0/6)

+			

+//ADDRESS:			

+DATA 4	0x020e0250 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS

+DATA 4	0x020e024c 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS

+DATA 4	0x020e0490 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS 

+			

+//Control:			

+DATA 4	0x020e0288 0x000C0030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET -- DRAM_RST: DDR3 SEL + pull down 100k (0x000C0030)

+DATA 4	0x020e0270 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be configured using Group Control Register: IOMUXC_SW_PAD_CTL_GRP_CTLDS

+DATA 4	0x020e0260 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0

+DATA 4	0x020e0264 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1

+DATA 4	0x020e04a0 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS 

+			

+//Data Strobes:			

+DATA 4	0x020e0494 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 

+DATA 4	0x020e0280 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 

+DATA 4	0x020e0284 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 

+			

+//Data:			

+DATA 4	0x020e04b0 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE

+DATA 4	0x020e0498 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS 

+DATA 4	0x020e04a4 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS 

+			

+DATA 4	0x020e0244 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0

+DATA 4	0x020e0248 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1

+			

+			

+//=============================================================================			

+// DDR Controller Registers			

+//=============================================================================			

+// Manufacturer:	Micron		

+// Device Part Number:	MT41K256M16TW-107		

+// Clock Freq.: 	400MHz		

+// Density per CS in Gb: 	4		

+// Chip Selects used:	1		

+// Number of Banks:	8		

+// Row address:    	15		

+// Column address: 	10		

+// Data bus width	16		

+//=============================================================================			

+DATA 4	0x021b001c 0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up

+			

+//=============================================================================			

+// Calibration setup.			

+//=============================================================================			

+DATA 4	0x021b0800 0xA1390003	// DDR_PHY_P0_MPZQHWCTRL, enable both one-time & periodic HW ZQ calibration.

+			

+// For target board, may need to run write leveling calibration to fine tune these settings.			

+DATA 4	0x021b080c  0x00000000	

+			

+//Read DQS Gating calibration			

+DATA 4	0x021b083c 0x014C0150 // 0x415C015C	 MPDGCTRL0 PHY0

+			

+//Read calibration			

+DATA 4	0x021b0848 0x4040464E // 0x40404244 MPRDDLCTL PHY0

+			

+//Write calibration                     			

+DATA 4	0x021b0850 0x4040564E // 0x40405A58	MPWRDLCTL PHY0

+			

+//read data bit delay: (3 is the reccommended default value, although out of reset value is 0)			

+DATA 4	0x021b081c 0x33333333	// MMDC_MPRDDQBY0DL

+DATA 4	0x021b0820 0x33333333	// MMDC_MPRDDQBY1DL

+			

+//write data bit delay: 			

+DATA 4	0x021b082c 0xF3333333	// MMDC_MPWRDQBY0DL

+DATA 4	0x021b0830 0xF3333333	// MMDC_MPWRDQBY1DL

+			

+//DQS&CLK Duty Cycle			

+DATA 4	0x021b08c0 0x00921012	// [MMDC_MPDCCR] MMDC Duty Cycle Control Register

+			

+// Complete calibration by forced measurement:                  			

+DATA 4	0x021b08b8 0x00000800	// DDR_PHY_P0_MPMUR0, frc_msr

+//=============================================================================			

+// Calibration setup end			

+//=============================================================================			

+			

+//MMDC init: 			

+DATA 4	0x021b0004 0x0002002D	// MMDC0_MDPDC

+DATA 4	0x021b0008 0x1B333030	// MMDC0_MDOTC

+DATA 4	0x021b000c 0x676B52F3	// MMDC0_MDCFG0

+DATA 4	0x021b0010 0xB66D0B63	// MMDC0_MDCFG1

+DATA 4	0x021b0014 0x01FF00DB	// MMDC0_MDCFG2

+			

+//MDMISC: RALAT kept to the high level of 5. 			

+//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits: 			

+//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			

+//b. Small performence improvment 			

+DATA 4	0x021b0018 0x00201740	// MMDC0_MDMISC

+DATA 4	0x021b001c 0x00008000	// MMDC0_MDSCR, set the Configuration request bit during MMDC set up

+DATA 4	0x021b002c 0x000026D2	// MMDC0_MDRWD

+DATA 4	0x021b0030 0x006B1023	// MMDC0_MDOR

+DATA 4	0x021b0040 0x0000004F	// Chan0 CS0_END 

+DATA 4	0x021b0000 0x84180000	// MMDC0_MDCTL

+			

+DATA 4	0x021b0890 0x00400000	// MPPDCMPR2

+			

+//Mode register writes                 			

+DATA 4	0x021b001c 0x02008032	// MMDC0_MDSCR, MR2 write, CS0

+DATA 4	0x021b001c 0x00008033	// MMDC0_MDSCR, MR3 write, CS0

+DATA 4	0x021b001c 0x00048031	// MMDC0_MDSCR, MR1 write, CS0

+DATA 4	0x021b001c 0x15208030	// MMDC0_MDSCR, MR0write, CS0

+DATA 4	0x021b001c 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0

+			

+//DATA 4	0x021b001c 0x0200803A	// MMDC0_MDSCR, MR2 write, CS1

+//DATA 4	0x021b001c 0x0000803B	// MMDC0_MDSCR, MR3 write, CS1

+//DATA 4	0x021b001c 0x00448039	// MMDC0_MDSCR, MR1 write, CS1

+//DATA 4	0x021b001c 0x15208038	// MMDC0_MDSCR, MR0write, CS1

+//DATA 4	0x021b001c 0x04008048	// MMDC0_MDSCR, ZQ calibration command sent to device on CS1

+			

+DATA 4	0x021b0020 0x00000800	// MMDC0_MDREF

+			

+DATA 4	0x021b0818 0x00000227	// DDR_PHY_P0_MPODTCTRL

+			

+DATA 4	0x021b0004 0x0002552D	// MMDC0_MDPDC now SDCTL power down enabled

+			

+DATA 4	0x021b0404 0x00011006	// MMDC0_MAPSR ADOPT power down enabled, MMDC will enter automatically to self-refresh while the number of idle cycle reached.

+			

+DATA 4	0x021b001c 0x00000000	// MMDC0_MDSCR, clear this register (especially the configuration bit as initialization is complete)

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

+			

diff --git a/board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg b/board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg
deleted file mode 100644
index aff2a2e..0000000
--- a/board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (C) 2016 ISEE 2007 SL - http://www.isee.biz
- *
- * SPDX-License-Identifier:	GPL-2.0+
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- */
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi, sd (the board has no nand neither onenand)
- */
-
-BOOT_FROM	sd
-
-#ifdef CONFIG_SECURE_BOOT
-CSF CONFIG_CSF_SIZE
-#endif
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-
-/* DDR type MT41K256M16TW-107 */
-
-//=============================================================================			
-// Enable all clocks (they are disabled by ROM code)			
-//=============================================================================	
-
-DATA 4 0x020c4068 0xffffffff    // CCM_CCGR0
-DATA 4 0x020c406c 0xffffffff    // CCM_CCGR1
-DATA 4 0x020c4070 0xffffffff    // CCM_CCGR2
-DATA 4 0x020c4074 0xffffffff    // CCM_CCGR3
-DATA 4 0x020c4078 0xffffffff    // CCM_CCGR4
-DATA 4 0x020c407c 0xffffffff    // CCM_CCGR5
-DATA 4 0x020c4080 0xffffffff    // CCM_CCGR6
-
-//=============================================================================			
-// IOMUX IMX6UL - MCIMX6G3CV
-//=============================================================================
-
-//DDR IO TYPE:				
-DATA 4 0x020E04B4 0x000C0000	// IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE
-DATA 4 0x020E04AC 0x00000000	// IOMUXC_SW_PAD_CTL_GRP_DDRPKE
-
-//CLOCK:			
-DATA 4 0x020E027C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P
-
-//ADDRESS:
-DATA 4 0x020E0250 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B			
-DATA 4 0x020E024C 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B
-DATA 4 0x020E0490 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_ADDDS
-
-//Control:
-DATA 4 0x020E0288 0x000C0030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET			
-DATA 4 0x020E0270 0x00000000	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2
-DATA 4 0x020E0260 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0
-DATA 4 0x020E0264 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1
-DATA 4 0x020E04A0 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_CTLDS
-
-//Data Strobes:
-DATA 4 0x020E0494 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL			
-DATA 4 0x020E0280 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P
-DATA 4 0x020E0284 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P
-
-//Data:
-DATA 4 0x020E04B0 0x00020000	// IOMUXC_SW_PAD_CTL_GRP_DDRMODE
-DATA 4 0x020E0498 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B0DS
-DATA 4 0x020E04A4 0x00000030	// IOMUXC_SW_PAD_CTL_GRP_B1DS
-
-DATA 4 0x020E0244 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0
-DATA 4 0x020E0248 0x00000030	// IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1
-
-//=============================================================================			
-// DDR Controller Registers			
-//=============================================================================			
-// Manufacturer:	Micron		
-// Device Part Number:  MT41K256M16TW-107		
-// Clock Freq.: 933 MHz	IMX6UL ensures data capture margin up to 400 Mhz	
-// Density per CS in Gb: 4 Gb		
-// Chip Selects used:	1		
-// Number of Banks:	8		
-// Row address:		15		
-// Column address:	10		
-// Data bus width	16		
-//=============================================================================
-
-DATA 4 0x021B001C 0x00008000    // MMDC0_MDSCR Set the Configuration request bit during MMDC set up
-			
-//=============================================================================			
-// Calibration setup.	REVISAR		
-//=============================================================================	
-
-DATA 4 0x021B0800 0xA1390003	// MMDC_MPZQHWCTRL Enable both one-time & periodic HW ZQ calibration.
-
-// For target board, may need to run write leveling calibration to fine tune these settings.			
-DATA 4 0x021B080C 0x00000000	// MMDC_MPWLDECTRL0
-
-// Read DQS Gating calibration
-DATA 4 0x021B083C 0x00000000	// MMDC_MPDGCTRL0
-
-// Read Calibration
-DATA 4 0x021B0848 0x40404040	// MMDC_MPRDDLCTL 0x40404244
-
-// Write Calibration
-DATA 4 0x021B0850 0x40404040	// MMDC_MPWRDLCTL 0x40405A58
-
-// Read Data bit delay
-DATA 4 0x021B081C 0x33333333	// MMDC_MPRDDQBY0DL
-DATA 4 0x021B0820 0x33333333	// MMDC_MPRDDQBY1DL
-DATA 4 0x021B082C 0xf3333333	// MMDC_MPWRDQBY0DL
-DATA 4 0x021B0830 0xf3333333	// MMDC_MPWRDQBY1DL
-
-// Control Duty Cicle DQS of and primary clock CK0
-DATA 4 0x021B08C0 0x24922492	// MMDC_MPDCCR 0x00921012 24922492 0x00921012
-
-// Complete Calibration by Forced Measurement
-DATA 4 0x021B08b8 0x00008000    // MMDC_MPMUR0
-
-//=============================================================================			
-// Calibration setup end			
-//=============================================================================	
-
-// MMCD Init
-DATA 4 0x021B0004 0x00020036	// MMDC_MDPDC 
-DATA 4 0x021B0008 0x00333030	// MMDC_MDOTC 
-DATA 4 0x021B000C 0x676B52F3	// MMDC_MDCFG0 
-DATA 4 0x021B0010 0xB66D0B63    // MMDC_MDCFG1
-DATA 4 0x021B0014 0x01FF00DB	// MMDC_MDCFG2
-
-//MDMISC: RALAT kept to the high level of 5.	
-//MDMISC: consider reducing RALAT if your 528MHz board design allow that. Lower RALAT benefits:
-//a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT to 3			
-//b. Small performence improvment 
-DATA 4 0x021B0018 0x00201740	// MMDC_MDMISC
-DATA 4 0x021B001C 0x00000800    // MMDC_MDSCR
-DATA 4 0x021B002C 0x000026D2	// MMDC_MDRWD
-DATA 4 0x021B0030 0x006B1023	// MMDC_MDOR
-DATA 4 0x021B0040 0x0000003F	// MMDC_MDASP Initial value 3f = 0 Mb, increments of 256 Mb
-DATA 4 0x021B0000 0x84180000	// MMDC_MDCTL
-
-// ????
-DATA 4 0x021B0890 0x00400000	// MMDC_MPPDCMPR2 DDR2 Only ???
-
-// Mode Register writes
-// MT41K64M16TW-107 is a DDR3 memory so there is no need to configure CS1, CS1 only used for LPDDR2 ??
-DATA 4 0x021B001C 0x02008032    // MMDC0_MDSCR, MR2 write, CS0
-DATA 4 0x021B001C 0x00008033	// MMDC0_MDSCR, MR3 write, CS0
-DATA 4 0x021B001C 0x00048031	// MMDC0_MDSCR, MR1 write, CS0
-DATA 4 0x021B001C 0x15208030	// MMDC0_MDSCR, MR0write, CS0
-DATA 4 0x021B001C 0x04008040	// MMDC0_MDSCR, ZQ calibration command sent to device on CS0
-
-
-DATA 4 0x021B0020 0x00000800    // MMDC0_MDREF
-
-DATA 4 0x021B0818 0x00000227	// DDR_PHY_P0_MPODTCTRL
-
-DATA 4 0x021B0004 0x0002556D	// MMDC0_MDPDC
-
-DATA 4 0x021B0404 0x00011006	// MMDC0_MAPSR
-
-DATA 4 0x021B001C 0x00000000	// MMDC0_MDSCR
diff --git a/board/isee/igep0146/mxul_igep0146_prcarlos.cfg b/board/isee/igep0146/mxul_igep0146_prcarlos.cfg
deleted file mode 100644
index 0ae8b0b..0000000
--- a/board/isee/igep0146/mxul_igep0146_prcarlos.cfg
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#define __ASSEMBLY__
-#include <config.h>
-
-/* image version */
-
-IMAGE_VERSION 2
-
-/*
- * Boot Device : one of
- * spi/sd/nand/onenand, qspi/nor
- */
-
-#ifdef CONFIG_QSPI_BOOT
-BOOT_FROM	qspi
-#else
-BOOT_FROM	sd
-#endif
-
-#ifdef CONFIG_USE_IMXIMG_PLUGIN
-/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
-PLUGIN  board/freescale/mx6sxsabresd/plugin.bin 0x00907000
-#else
-
-#ifdef CONFIG_SECURE_BOOT
-CSF CONFIG_CSF_SIZE
-#endif
-
-/*
- * Device Configuration Data (DCD)
- *
- * Each entry must have the format:
- * Addr-type           Address        Value
- *
- * where:
- *	Addr-type register length (1,2 or 4 bytes)
- *	Address	  absolute address of the register
- *	value	  value to be stored in the register
- */
-
-/* Enable all clocks */
-DATA 4 0x020c4068 0xffffffff
-DATA 4 0x020c406c 0xffffffff
-DATA 4 0x020c4070 0xffffffff
-DATA 4 0x020c4074 0xffffffff
-DATA 4 0x020c4078 0xffffffff
-DATA 4 0x020c407c 0xffffffff
-DATA 4 0x020c4080 0xffffffff
-DATA 4 0x020c4084 0xffffffff
-
-/* IOMUX - DDR IO Type */
-DATA 4 0x020e0618 0x000c0000
-DATA 4 0x020e05fc 0x00000000
-
-/* Clock */
-DATA 4 0x020e032c 0x00000030
-
-/* Address */
-DATA 4 0x020e0300 0x00000020
-DATA 4 0x020e02fc 0x00000020
-DATA 4 0x020e05f4 0x00000020
-
-/* Control */
-DATA 4 0x020e0340 0x00000020
-
-DATA 4 0x020e0320 0x00000000
-DATA 4 0x020e0310 0x00000020
-DATA 4 0x020e0314 0x00000020
-DATA 4 0x020e0614 0x00000020
-
-/* Data Strobe */
-DATA 4 0x020e05f8 0x00020000
-DATA 4 0x020e0330 0x00000028
-DATA 4 0x020e0334 0x00000028
-DATA 4 0x020e0338 0x00000028
-DATA 4 0x020e033c 0x00000028
-
-/* Data */
-DATA 4 0x020e0608 0x00020000
-DATA 4 0x020e060c 0x00000028
-DATA 4 0x020e0610 0x00000028
-DATA 4 0x020e061c 0x00000028
-DATA 4 0x020e0620 0x00000028
-DATA 4 0x020e02ec 0x00000028
-DATA 4 0x020e02f0 0x00000028
-DATA 4 0x020e02f4 0x00000028
-DATA 4 0x020e02f8 0x00000028
-
-/* Calibrations - ZQ */
-DATA 4 0x021b0800 0xa1390003
-
-/* Write leveling */
-DATA 4 0x021b080c 0x00290025
-DATA 4 0x021b0810 0x00220022
-
-/* DQS Read Gate */
-DATA 4 0x021b083c 0x41480144
-DATA 4 0x021b0840 0x01340130
-
-/* Read/Write Delay */
-DATA 4 0x021b0848 0x3C3E4244
-DATA 4 0x021b0850 0x34363638
-
-/* Read data bit delay */
-DATA 4 0x021b081c 0x33333333
-DATA 4 0x021b0820 0x33333333
-DATA 4 0x021b0824 0x33333333
-DATA 4 0x021b0828 0x33333333
-
-/* Complete calibration by forced measurement */
-DATA 4 0x021b08b8 0x00000800
-
-/* MMDC init - DDR3, 64-bit mode, only MMDC0 is initiated */
-DATA 4 0x021b0004 0x0002002d
-DATA 4 0x021b0008 0x00333030
-DATA 4 0x021b000c 0x676b52f3
-DATA 4 0x021b0010 0xb66d8b63
-DATA 4 0x021b0014 0x01ff00db
-DATA 4 0x021b0018 0x00011740
-DATA 4 0x021b001c 0x00008000
-DATA 4 0x021b002c 0x000026d2
-DATA 4 0x021b0030 0x006b1023
-DATA 4 0x021b0040 0x0000005f
-DATA 4 0x021b0000 0x84190000
-
-/* Initialize MT41K256M16HA-125 - MR2 */
-DATA 4 0x021b001c 0x04008032
-/* MR3 */
-DATA 4 0x021b001c 0x00008033
-/* MR1 */
-DATA 4 0x021b001c 0x00048031
-/* MR0 */
-DATA 4 0x021b001c 0x05208030
-/* DDR device ZQ calibration */
-DATA 4 0x021b001c 0x04008040
-
-/* Final DDR setup, before operation start */
-DATA 4 0x021b0020 0x00000800
-DATA 4 0x021b0818 0x00011117
-DATA 4 0x021b001c 0x00000000
-#endif
diff --git a/configs/igep0146_imx6ul_512M_defconfig b/configs/igep0146_imx6ul_512M_defconfig
index d3f6b9e..9df7c91 100644
--- a/configs/igep0146_imx6ul_512M_defconfig
+++ b/configs/igep0146_imx6ul_512M_defconfig
@@ -1,4 +1,4 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg,MX6UL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0146/mx6ul_igep0146_1x512.cfg,MX6UL"
 CONFIG_ARM=y
 CONFIG_ARCH_MX6=y
 CONFIG_MX6UL=y
@@ -13,4 +13,12 @@ CONFIG_CMD_CACHE=y
 CONFIG_OF_LIBFDT=y
 CONFIG_DM=y
 CONFIG_DM_THERMAL=y
-CONFIG_DISPLAY_BOARDINFO=y
\ No newline at end of file
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_DEFAULT_FDT_FILE="imx6ul-igep-base0040rd102.dtb"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
diff --git a/configs/igep0146_imx6ul_512M_spl_defconfig b/configs/igep0146_imx6ul_512M_spl_defconfig
new file mode 100644
index 0000000..e0fa901
--- /dev/null
+++ b/configs/igep0146_imx6ul_512M_spl_defconfig
@@ -0,0 +1,28 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0146/mx6ul_igep0146_1x512_nt.cfg,MX6UL"
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_MX6UL=y
+CONFIG_TARGET_IGEP0146=y
+CONFIG_BOOTDELAY=3
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_MEMTEST=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_LIBFDT=y
+CONFIG_DM=y
+CONFIG_DM_THERMAL=y
+CONFIG_DISPLAY_BOARDINFO=y
+
+CONFIG_SPL=y
+CONFIG_SPL_BUILD=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
diff --git a/include/configs/igep0146.h b/include/configs/igep0146.h
index 2819086..5638c00 100644
--- a/include/configs/igep0146.h
+++ b/include/configs/igep0146.h
@@ -14,15 +14,14 @@
 #include "mx6_common.h"	
 
 
-#define CONFIG_SECURE_BOOT
 #ifdef CONFIG_SECURE_BOOT
 #ifndef CONFIG_CSF_SIZE
 #define CONFIG_CSF_SIZE 0x4000
+#define CONFIG_SYS_FSL_SEC_COMPAT    4 /* HAB version */
+#define CONFIG_FSL_CAAM
 #endif
 #endif
 
-#define CONFIG_SYS_FSL_SEC_COMPAT    4 /* HAB version */
-#define CONFIG_FSL_CAAM
 
 /* Falcon Mode */
 #ifdef CONFIG_SPL
@@ -51,7 +50,7 @@
 /* UART Configs */
 #define CONFIG_MXC_UART
 #define CONFIG_MXC_UART_BASE		UART3_BASE
-#define CONSOLE_DEV					"ttymxc1"
+#define CONSOLE_DEV					"ttymxc2"
 #define CONFIG_BAUDRATE				115200
 #define CONFIG_SYS_BAUDRATE_TABLE	{9600, 19200, 38400, 57600, 115200}
 
@@ -79,7 +78,7 @@
 
 
 /* Miscellaneous configurable options */
-#define CONFIG_AUTOBOOT_KEYED
+/*#define CONFIG_AUTOBOOT_KEYED*/
 #define CONFIG_AUTOBOOT_PROMPT "Press ESC to abort autoboot in %d seconds\n"
 #define CONFIG_AUTOBOOT_STOP_STR "\x1b"
 #define CONFIG_SYS_LONGHELP
@@ -88,20 +87,47 @@
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_STACKSIZE               (128 * 1024)
 
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
+#define CONFIG_SYS_I2C_SPEED		100000
+
+/* EEPROM Configs */
+#define CONFIG_SYS_I2C_EEPROM_BUS	1
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
+
 /* MMC Configs */
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
-#define CONFIG_SYS_FSL_ESDHC_ADDR	0
+#define CONFIG_SYS_FSL_ESDHC_ADDR	USDHC2_BASE_ADDR
 #define CONFIG_SYS_FSL_USDHC_NUM	2
-#define CONFIG_DOS_PARTITION
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
 
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_FAT_WRITE
 
+/* Network */
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+
+#define IMX_FEC_BASE			ENET_BASE_ADDR
+#define CONFIG_FEC_MXC_PHYADDR          0x1
+
+#define CONFIG_FEC_XCV_TYPE             RMII
+#define CONFIG_ETHPRIME                 "FEC"
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+#define CONFIG_RESET_PHY_R			/* Software Reset of PHY */
 
-/* NET Configs */
-#define CONFIG_ENV_OVERWRITE		/* To allow write MAC into ethaddr variable */
 
 /* Environment */
 #define CONFIG_ENV_SIZE			(128 * 1024)
@@ -109,13 +135,168 @@
 #define CONFIG_SYS_MMC_ENV_DEV		0
 
 /* Commands */
+#define CONFIG_CMD_BOOTZ
 #undef 	CONFIG_CMD_IMLS
 #define EMMC_ENV ""
 #define VIDEO_ARGS ""
 #define VIDEO_ARGS_SCRIPT ""
 
+#define EMMC_ENV ""
+
+#ifndef VIDEO_ARGS
+#define VIDEO_ARGS ""
+#endif
+
+#ifndef VIDEO_ARGS_SCRIPT
+#define VIDEO_ARGS_SCRIPT ""
+#endif
 
-#endif                         /* __IGEP0046_CONFIG_H */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootenv=uEnv.txt\0" \
+	"image=zImage\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x83000000\0" \
+	"boot_fdt=try\0" \
+	"ipaddr=192.168.2.110\0" \
+	"ip_dyn=no\0" \
+	"console=" CONSOLE_DEV "\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"initrd_high=0xffffffff\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0" \
+	"mmcroot="CONFIG_MMCROOT " rootwait rw\0" \
+	"emmcroot=/dev/mmcblk2p2 rootwait rw\0" \
+	"sataroot=/dev/sda2 rw rootwait\0" \
+	"emmcdevconf=setenv mmcdev ${emmcdev}\0" \
+	"emmcrootconf=setenv mmcroot ${emmcroot}\0" \
+	"update_sd_firmware=" \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"if mmc dev ${mmcdev}; then "	\
+			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
+				"setexpr fw_sz ${filesize} / 0x200; " \
+				"setexpr fw_sz ${fw_sz} + 1; "	\
+				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
+			"fi; "	\
+		"fi\0" \
+	EMMC_ENV	  \
+	"video_args_hdmi=setenv video_args $video_args " \
+		"video=mxcfb${fb}:dev=hdmi,1920x1080M@60,if=RGB24\0" \
+	"video_args_lvds=setenv video_args $video_args " \
+		"video=mxcfb${fb}:dev=ldb,1280x720M@60,if=RGB24\0" \
+	"fb=0\0" \
+	"video_interfaces=hdmi lvds\0" \
+	"video_args_script=" \
+		"for v in ${video_interfaces}; do " \
+			"run video_args_${v}; " \
+			"setexpr fb $fb + 1; " \
+		"done\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot} " \
+		VIDEO_ARGS "\0" \
+	"loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0" \
+	"importbootenv=echo Importing environment from mmc ...; " \
+		"env import -t ${loadaddr} ${filesize}\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		VIDEO_ARGS_SCRIPT \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"sataargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${sataroot} " \
+		VIDEO_ARGS "\0" \
+	"loadimagesata=fatload sata 0:1 ${loadaddr}  ${image}\0" \
+	"loadfdtsata=fatload sata 0:1 ${fdt_addr} ${fdt_file}\0" \
+	"sataboot=echo Booting from sata ...; " \
+		VIDEO_ARGS_SCRIPT \
+		"run sataargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdtsata; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if run loadfdtsata; then " \
+					"bootz ${loadaddr} - ${fdt_addr}; " \
+				"else " \
+					"if test ${boot_fdt} = try; then " \
+						"bootz; " \
+					"else " \
+						"echo WARN: Cannot load the DT; " \
+					"fi; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+	"netargs=setenv bootargs console=${console},${baudrate} " \
+		"root=/dev/nfs " \
+		"ip=dhcp nfsroot=${serverip}:${rootnfs},v3,tcp\0" \
+	"netboot=echo Booting from net ...; " \
+		"run netargs; " \
+		"ping ${serverip}; " \
+		"if test ${ip_dyn} = yes; then " \
+			"setenv get_cmd dhcp; " \
+		"else " \
+			"setenv get_cmd tftp; " \
+		"fi; " \
+		"${get_cmd} ${image}; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+	"echo Try first mmc (SD)...; " \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if run loadimage; then " \
+			"run mmcboot; " \
+		"fi; " \
+	"fi; " \
+	"echo Try second mmc (eMMC)...; " \
+	"run emmcdevconf;" \
+	"run emmcrootconf;" \
+	"mmc dev ${mmcdev};" \
+	"if mmc rescan; then " \
+		"if run loadbootenv; then " \
+			"echo Loaded environment from ${bootenv};" \
+			"run importbootenv;" \
+		"fi;" \
+		"if run loadimage; then " \
+			"run mmcboot; " \
+		"fi; " \
+	"fi; " \
+	"run netboot;"
+
+#endif                         /* __IGEP0146_CONFIG_H */