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| author | Ye Li <ye.li@nxp.com> | 2017-04-14 13:44:48 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-14 14:04:30 +0800 |
| commit | b1d2ec2d646c5802ebdbbe6f1526c28a1f881933 (patch) | |
| tree | f75037afe62f310407ccb4ca49b69ddafb82052c | |
| parent | e72f766c98a3df9b620feb51484e33c7d50bed3c (diff) | |
| download | u-boot-imx-b1d2ec2d646c5802ebdbbe6f1526c28a1f881933.zip u-boot-imx-b1d2ec2d646c5802ebdbbe6f1526c28a1f881933.tar.gz u-boot-imx-b1d2ec2d646c5802ebdbbe6f1526c28a1f881933.tar.bz2 | |
MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0
The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to
workaround PLL issue.
When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal.
raise: Signal # 8 caught
To avoid such problem, we change our calculation.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f28cf489e1b3864bac6bae4944d8a73bab30ec32)
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/scg.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c index 77ab1a9..6eadd48 100644 --- a/arch/arm/cpu/armv7/mx7ulp/scg.c +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -507,7 +507,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_A7_APLL: reg = readl(&scg1_regs->apllcsr); @@ -536,7 +539,10 @@ u32 decode_pll(enum pll_clocks pll) infreq = infreq / pre_div; - return infreq * mult + infreq * num / denom; + if (denom) + return infreq * mult + infreq * num / denom; + else + return infreq * mult; case PLL_USB: reg = readl(&scg1_regs->upllcsr); |