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| author | Ye Li <ye.li@nxp.com> | 2017-07-24 01:12:33 -0500 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-07-25 00:20:46 -0500 |
| commit | 922168448596a075c8b990bea3a81bcb62024ae4 (patch) | |
| tree | 5298698c890c5585426055eb88b6cd2373ca6d8c | |
| parent | c7aefcba1d8eaa503c7e7dc108c097ae4a1a9a95 (diff) | |
| download | u-boot-imx-922168448596a075c8b990bea3a81bcb62024ae4.zip u-boot-imx-922168448596a075c8b990bea3a81bcb62024ae4.tar.gz u-boot-imx-922168448596a075c8b990bea3a81bcb62024ae4.tar.bz2 | |
MLK-16069 imx6slevk: Workaround to limit the u-boot in low 512MB memory
On i.MX6SLEVK board, the LPDDR2 chip(CS1) is not reset before accessing.
And due to MMDC limitation, the script we get from IC team is only doing
CS0 reset but skipping CS1 reset, the reason is that doing CS1 reset might
cause CS0 can NOT be accessed any longer.
Because of this HW issue, we found the high 512MB memory needs more time to
be stable. Since the u-boot relocates itself to highest address after booting,
so this will cause issue.
To work around it, we just limit the u-boot running at low 512MB memory.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5fc93379dc3576ee9dc00f108bc18d8d6059d9c3)
| -rw-r--r-- | board/freescale/mx6slevk/mx6slevk.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/board/freescale/mx6slevk/mx6slevk.c b/board/freescale/mx6slevk/mx6slevk.c index 7a11f13..3c9e073 100644 --- a/board/freescale/mx6slevk/mx6slevk.c +++ b/board/freescale/mx6slevk/mx6slevk.c @@ -85,6 +85,17 @@ int dram_init(void) return 0; } +phys_size_t get_effective_memsize(void) +{ + return SZ_512M; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} + static iomux_v3_cfg_t const uart1_pads[] = { MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |