MLK-14484-2 mx7ulp_arm2: Add 10x10 and 14x14 ARM2 codes

Copy the mx7ulp ARM2 codes from v2016.03 as the base for using
OF_CONTROL and DM drivers.

The 14x14 ARM2 LPDDR3 script is v1.5:
- IMX7ULP1_LPDDR3_320MHz_512MB_32bit_V1.5.inc

The 10x10 ARM2 LPDDR2 script is v1.1:
- IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.1.inc

Signed-off-by: Ye Li <ye.li@nxp.com>

10 files changed, 1232 insertions, 0 deletions

diff --git a/arch/arm/cpu/armv7/mx7ulp/Kconfig b/arch/arm/cpu/armv7/mx7ulp/Kconfig
index 284f9ff..fc7159e 100644
--- a/arch/arm/cpu/armv7/mx7ulp/Kconfig
+++ b/arch/arm/cpu/armv7/mx7ulp/Kconfig
@@ -16,12 +16,21 @@ choice
 	prompt "MX7ULP board select"
 	optional
 
+config TARGET_MX7ULP_10X10_ARM2
+	bool "Support mx7ulp 10x10 validation board"
+	select MX7ULP
+
+config TARGET_MX7ULP_14X14_ARM2
+	bool "Support mx7ulp 14x14 validation board"
+	select MX7ULP
+
 config TARGET_MX7ULP_EVK
         bool "Support mx7ulp EVK board"
 	select MX7ULP
 
 endchoice
 
+source "board/freescale/mx7ulp_arm2/Kconfig"
 source "board/freescale/mx7ulp_evk/Kconfig"
 
 endif
diff --git a/board/freescale/mx7ulp_arm2/Kconfig b/board/freescale/mx7ulp_arm2/Kconfig
new file mode 100644
index 0000000..7fa0c0b
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_MX7ULP_10X10_ARM2 || TARGET_MX7ULP_14X14_ARM2
+
+config SYS_BOARD
+	default "mx7ulp_arm2"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_CONFIG_NAME
+	default "mx7ulp_arm2"
+
+endif
diff --git a/board/freescale/mx7ulp_arm2/Makefile b/board/freescale/mx7ulp_arm2/Makefile
new file mode 100644
index 0000000..57e795a
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/Makefile
@@ -0,0 +1,6 @@
+# (C) Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y  := mx7ulp_arm2.o
diff --git a/board/freescale/mx7ulp_arm2/imximage.cfg b/board/freescale/mx7ulp_arm2/imximage.cfg
new file mode 100644
index 0000000..c04d5e0
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/imximage.cfg
@@ -0,0 +1,119 @@
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x00000180
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x39373939
+DATA 4   0x40AB0850 0x2F313D36
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x424642F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DA
+DATA 4   0x40AB0018 0x00211718
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000004F
+DATA 4   0x40AB0000 0x84190000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x83018030
+DATA 4   0x40AB001C 0x01038030
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1310003
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg b/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg
new file mode 100644
index 0000000..51f1be2
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg
@@ -0,0 +1,127 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x0000018C
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
new file mode 100644
index 0000000..84a5f11
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mx7ulp-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/gpio.h>
+#include <fsl_esdhc.h>
+#include <mmc.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ESDHC_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+#define ESDHC_CD_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE | PAD_CTL_PUS_UP)
+
+#define UART_PAD_CTRL	(PAD_CTL_PUS_UP)
+
+#define GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE)
+
+#define OTG_ID_GPIO_PAD_CTRL	(PAD_CTL_IBE_ENABLE)
+#define OTG_PWR_GPIO_PAD_CTRL	(PAD_CTL_OBE_ENABLE)
+
+#define QSPI_PAD_CTRL1	(PAD_CTL_PUS_UP | PAD_CTL_DSE)
+
+#define QSPI_PAD_CTRL0	(PAD_CTL_PUS_UP | PAD_CTL_DSE \
+	| PAD_CTL_OBE_ENABLE)
+
+
+int dram_init(void)
+{
+    gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+static int mx7ulp_board_rev(void)
+{
+	return 0x41;
+}
+
+u32 get_board_rev(void)
+{
+	int rev = mx7ulp_board_rev();
+
+	return (get_cpu_rev() & ~(0xF << 8)) | rev;
+}
+
+static iomux_cfg_t const lpuart4_pads[] = {
+    MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+    MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+/* PTF11 and PTF10 also can mux to LPUART6 on 10x10 ARM2, depends on rework*/
+static iomux_cfg_t const lpuart6_pads[] = {
+    MX7ULP_PAD_PTE11__LPUART6_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+    MX7ULP_PAD_PTE10__LPUART6_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+	mx7ulp_iomux_setup_multiple_pads(lpuart6_pads, ARRAY_SIZE(lpuart4_pads));
+#else
+    mx7ulp_iomux_setup_multiple_pads(lpuart4_pads, ARRAY_SIZE(lpuart4_pads));
+#endif
+}
+
+#ifdef CONFIG_USB_EHCI_MX7
+
+static iomux_cfg_t const usb_otg1_pads[] = {
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+	MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL),  /* gpio for otgid */
+	MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL),  /* gpio for power en */
+#else
+	/*Need rework for ID and PWR_EN pins on 14x14 ARM2*/
+	MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL),  /* gpio for otgid */
+	MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL),  /* gpio for power en */
+#endif
+};
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+#define OTG0_ID_GPIO	IMX_GPIO_NR(3, 0)
+#define OTG0_PWR_EN		IMX_GPIO_NR(3, 1)
+#else
+#define OTG0_ID_GPIO	IMX_GPIO_NR(3, 18)
+#define OTG0_PWR_EN		IMX_GPIO_NR(1, 31)
+#endif
+static void setup_usb(void)
+{
+	mx7ulp_iomux_setup_multiple_pads(usb_otg1_pads,
+						 ARRAY_SIZE(usb_otg1_pads));
+
+	gpio_request(OTG0_ID_GPIO, "otg_id");
+	gpio_direction_input(OTG0_ID_GPIO);
+}
+
+/*Needs to override the ehci power if controlled by GPIO */
+int board_ehci_power(int port, int on)
+{
+	switch (port) {
+	case 0:
+		if (on)
+			gpio_direction_output(OTG0_PWR_EN, 1);
+		else
+			gpio_direction_output(OTG0_PWR_EN, 0);
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int board_usb_phy_mode(int port)
+{
+	int ret = 0;
+
+	if (port == 0) {
+		ret = gpio_get_value(OTG0_ID_GPIO);
+
+		if (ret)
+			return USB_INIT_DEVICE;
+		else
+			return USB_INIT_HOST;
+	}
+
+	return USB_INIT_HOST;
+}
+
+#endif
+
+
+int board_early_init_f(void)
+{
+	setup_iomux_uart();
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB14__QSPIA_SS1_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX7ULP_PAD_PTB5__PTB5 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define QSPI_RST_GPIO	IMX_GPIO_NR(2, 5)
+#else
+/* MT35XU512ABA supports 8 bits I/O, since our driver only support 4, so mux 4 data pins*/
+static iomux_cfg_t const quadspi_pads[] = {
+	MX7ULP_PAD_PTB8__QSPIA_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB9__QSPIA_DQS   | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB15__QSPIA_SCLK  | MUX_PAD_CTRL(QSPI_PAD_CTRL0),
+	MX7ULP_PAD_PTB16__QSPIA_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB17__QSPIA_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB18__QSPIA_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+	MX7ULP_PAD_PTB19__QSPIA_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL1),
+
+	MX7ULP_PAD_PTB12__PTB12 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+#define QSPI_RST_GPIO	IMX_GPIO_NR(2, 12)
+
+#endif
+int board_qspi_init(void)
+{
+	u32 val;
+	mx7ulp_iomux_setup_multiple_pads(quadspi_pads, ARRAY_SIZE(quadspi_pads));
+	/* enable clock */
+	val = readl(PCC1_RBASE + 0x94);
+
+	if (!(val & 0x20000000)) {
+		writel(0x03000003, (PCC1_RBASE + 0x94));
+		writel(0x43000003, (PCC1_RBASE + 0x94));
+	}
+
+	gpio_request(QSPI_RST_GPIO, "qspi_reset");
+	gpio_direction_output(QSPI_RST_GPIO, 0);
+	mdelay(10);
+	gpio_direction_output(QSPI_RST_GPIO, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	/* address of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_USB_EHCI_MX7
+	setup_usb();
+#endif
+
+#ifdef CONFIG_FSL_QSPI
+	board_qspi_init();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_FSL_ESDHC
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC0_RBASE, 0, 8},
+	{USDHC1_RBASE, 0},
+};
+
+static iomux_cfg_t const usdhc0_emmc_pads[] = {
+	MX7ULP_PAD_PTD0__SDHC0_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD1__SDHC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD2__SDHC0_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD3__SDHC0_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD4__SDHC0_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD5__SDHC0_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD6__SDHC0_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD7__SDHC0_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD8__SDHC0_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD9__SDHC0_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD10__SDHC0_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTD11__SDHC0_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+};
+
+static iomux_cfg_t const usdhc1_pads[] = {
+	MX7ULP_PAD_PTE11__SDHC1_RESET_b | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE3__SDHC1_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE2__SDHC1_CLK | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE9__SDHC1_D7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE8__SDHC1_D6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE7__SDHC1_D5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE6__SDHC1_D4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE4__SDHC1_D3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE5__SDHC1_D2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE0__SDHC1_D1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE1__SDHC1_D0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+    MX7ULP_PAD_PTE10__SDHC1_DQS | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
+
+	MX7ULP_PAD_PTE13__PTE13 | MUX_PAD_CTRL(ESDHC_CD_GPIO_PAD_CTRL),  /*CD*/
+};
+
+#define USDHC0_CD_GPIO	IMX_GPIO_NR(5, 13)
+
+int board_mmc_init(bd_t *bis)
+{
+	int i, ret;
+	/*
+	 * According to the board_mmc_init() the following map is done:
+	 * (U-Boot device node)    (Physical Port)
+	 * mmc0                    USDHC0
+	 * mmc1                    USDHC1
+	 */
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			mx7ulp_iomux_setup_multiple_pads(usdhc0_emmc_pads, ARRAY_SIZE(usdhc0_emmc_pads));
+			init_clk_usdhc(0);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+
+			break;
+		case 1:
+			mx7ulp_iomux_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+			init_clk_usdhc(1);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+
+			gpio_request(USDHC0_CD_GPIO, "usdhc1_cd");
+			gpio_direction_input(USDHC0_CD_GPIO);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return -EINVAL;
+			}
+
+			ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
+			if (ret)
+				return ret;
+	}
+
+	return 0;
+}
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC0_RBASE:
+		ret = 1;
+		break;
+	case USDHC1_RBASE:
+		ret = !gpio_get_value(USDHC0_CD_GPIO);
+		break;
+	}
+	return ret;
+}
+#endif
+
+
+int board_late_init(void)
+{
+    return 0;
+}
+
+int checkboard(void)
+{
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+	printf("Board: i.MX7ULP 10x10 ARM2 board\n");
+#else
+	printf("Board: i.MX7ULP 14x14 ARM2 board\n");
+#endif
+	return 0;
+}
diff --git a/board/freescale/mx7ulp_arm2/plugin.S b/board/freescale/mx7ulp_arm2/plugin.S
new file mode 100644
index 0000000..4e4b8bd
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/plugin.S
@@ -0,0 +1,334 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+.macro imx7ulp_ddr_freq_decrease
+	ldr r2, =0x403f0000
+	ldr r3, =0x00000000
+	str r3, [r2, #0xe0]
+
+	ldr r2, =0x403e0000
+	ldr r3, =0x01000020
+	str r3, [r2, #0x40]
+
+	ldr r3, =0x80808080
+	str r3, [r2, #0x50c]
+	ldr r3, =0x8080801E
+	str r3, [r2, #0x50c]
+
+	ldr r3, =0x00000040
+wait2:
+	ldr r4, [r2, #0x50c]
+	and r4, r3
+	cmp r4, r3
+	bne wait2
+
+	ldr r3, =0x00000001
+	str r3, [r2, #0x30]
+	ldr r3, =0x11000020
+	str r3, [r2, #0x40]
+
+	ldr r2, =0x403f0000
+	ldr r3, =0x42000000
+	str r3, [r2, #0xe0]
+
+.endm
+
+.macro imx7ulp_arm2_lpddr3_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x39373939
+	str r1, [r0, #0x848]
+	ldr r1, =0x2F313D36
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x424642F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DA
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211718
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000004F
+	str r1, [r0, #0x40]
+	ldr r1, =0x84190000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x83018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1310003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+.macro imx7ulp_arm2_lpddr2_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x40404040
+	str r1, [r0, #0x848]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x292C42F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211708
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000003F
+	str r1, [r0, #0x40]
+	ldr r1, =0xC3110000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x00008018
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+
+.macro imx7ulp_clock_gating
+.endm
+
+.macro imx7ulp_qos_setting
+.endm
+
+.macro imx7ulp_ddr_setting
+#if defined (CONFIG_TARGET_MX7ULP_10X10_ARM2)
+	imx7ulp_arm2_lpddr2_setting
+#else
+	imx7ulp_arm2_lpddr3_setting
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx7ulp_plugin.S>
diff --git a/configs/mx7ulp_10x10_arm2_defconfig b/configs/mx7ulp_10x10_arm2_defconfig
new file mode 100644
index 0000000..e0875b2
--- /dev/null
+++ b/configs/mx7ulp_10x10_arm2_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_TARGET_MX7ULP_10X10_ARM2=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_IMX_RGPIO2P=y
diff --git a/configs/mx7ulp_14x14_arm2_defconfig b/configs/mx7ulp_14x14_arm2_defconfig
new file mode 100644
index 0000000..25eb39d
--- /dev/null
+++ b/configs/mx7ulp_14x14_arm2_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_TARGET_MX7ULP_14X14_ARM2=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_IMX_RGPIO2P=y
diff --git a/include/configs/mx7ulp_arm2.h b/include/configs/mx7ulp_arm2.h
new file mode 100644
index 0000000..d3d601b
--- /dev/null
+++ b/include/configs/mx7ulp_arm2.h
@@ -0,0 +1,278 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX7ULP ARM2 board.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __MX7ULP_ARM2_CONFIG_H
+#define __MX7ULP_ARM2_CONFIG_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+/*Uncomment it to use plugin boot*/
+/*#define CONFIG_USE_PLUGIN*/
+
+/*Uncomment it to use secure boot*/
+/*#define CONFIG_SECURE_BOOT*/
+
+#ifdef CONFIG_SECURE_BOOT
+#ifndef CONFIG_CSF_SIZE
+#define CONFIG_CSF_SIZE 0x4000
+#endif
+#endif
+
+#define CONFIG_SYS_VSNPRINTF
+#define CONFIG_BOARD_POSTCLK_INIT
+#define CONFIG_IMX_FIXED_IVT_OFFSET
+#define CONFIG_SYS_BOOTM_LEN   0x1000000
+
+#define SRC_BASE_ADDR           CMC1_RBASE
+#define IRAM_BASE_ADDR          OCRAM_0_BASE
+#define IOMUXC_BASE_ADDR        IOMUXC1_RBASE
+
+/* Fuses */
+#define CONFIG_CMD_FUSE
+#define CONFIG_MXC_OCOTP
+
+/* MMC Configs */
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+#define CONFIG_SYS_FSL_ESDHC_ADDR       0
+#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
+#define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
+#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
+#define CONFIG_SYS_MMC_IMG_LOAD_PART	1
+
+#define CONFIG_ENV_OFFSET		(12 * SZ_64K)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_SIZE			SZ_8K
+
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR		 WDG1_RBASE
+#define CONFIG_ULP_WATCHDOG
+
+
+#define CONFIG_SYS_ARCH_TIMER
+#define CONFIG_SYS_HZ_CLOCK 1000000 /* Fixed at 1Mhz from TSTMR */
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* uncomment for PLUGIN mode support */
+/* #define CONFIG_USE_PLUGIN */
+
+/* uncomment for SECURE mode support */
+/* #define CONFIG_SECURE_BOOT */
+
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+/*#define CONFIG_REVISION_TAG*/
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(8 * SZ_1M)
+
+#define CONFIG_BOARD_LATE_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* UART */
+#define CONFIG_FSL_LPUART
+#define CONFIG_LPUART_32LE_REG
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+#define LPUART_BASE     LPUART6_RBASE
+#else
+#define LPUART_BASE     LPUART4_RBASE
+#endif
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_BAUDRATE			115200
+
+
+#undef CONFIG_CMD_IMLS
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_HUSH_PARSER
+
+#define CONFIG_BOOTDELAY		1
+#define CONFIG_SYS_CACHELINE_SIZE      64
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		512
+
+/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS		256
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE		SZ_8K
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_TEXT_BASE        0x67800000
+#define PHYS_SDRAM			        0x60000000
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+#define PHYS_SDRAM_SIZE			    SZ_1G   /*LPDDR2 1G*/
+#define CONFIG_SYS_MEMTEST_END      0x9E000000
+#else
+#define PHYS_SDRAM_SIZE			    SZ_512M
+#define CONFIG_SYS_MEMTEST_END      0x7E000000
+#endif
+#define CONFIG_SYS_MEMTEST_START    PHYS_SDRAM
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM
+#define CONFIG_CMD_BOOTZ
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_LOADADDR             0x60800000
+
+#define CONFIG_CMD_MEMTEST
+
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+#define CONFIG_DEFAULT_FDT_FILE		"imx7ulp-10x10-arm2.dtb"
+#else
+#define CONFIG_DEFAULT_FDT_FILE		"imx7ulp-14x14-arm2.dtb"
+#endif
+
+#define CONFIG_MFG_NAND_PARTITION
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		CONFIG_MFG_NAND_PARTITION \
+		"\0" \
+		"initrd_addr=0x63800000\0" \
+		"initrd_high=0xffffffff\0" \
+		"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"script=boot.scr\0" \
+	"image=zImage\0" \
+	"console=ttyLP0\0" \
+	"fdt_high=0xffffffff\0" \
+	"initrd_high=0xffffffff\0" \
+	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
+	"fdt_addr=0x63000000\0" \
+	"boot_fdt=try\0" \
+	"earlycon=lpuart32,0x402D0010\0" \
+	"ip_dyn=yes\0" \
+	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
+	"mmcargs=setenv bootargs console=${console},${baudrate} " \
+		"root=${mmcroot}\0" \
+	"loadbootscript=" \
+		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source\0" \
+	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+			"if run loadfdt; then " \
+				"bootz ${loadaddr} - ${fdt_addr}; " \
+			"else " \
+				"if test ${boot_fdt} = try; then " \
+					"bootz; " \
+				"else " \
+					"echo WARN: Cannot load the DT; " \
+				"fi; " \
+			"fi; " \
+		"else " \
+			"bootz; " \
+		"fi;\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	   "mmc dev ${mmcdev}; if mmc rescan; then " \
+		   "if run loadbootscript; then " \
+			   "run bootscript; " \
+		   "else " \
+			   "if run loadimage; then " \
+				   "run mmcboot; " \
+			   "fi; " \
+		   "fi; " \
+	   "fi"
+
+
+#define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	SZ_256K
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+/* USB Configs */
+#define CONFIG_CMD_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_MX7
+#define CONFIG_USB_STORAGE
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_ASIX
+#define CONFIG_MXC_USB_PORTSC  (PORT_PTS_UTMI | PORT_PTS_PTW)
+#define CONFIG_MXC_USB_FLAGS   0
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
+/* QSPI configs */
+#define CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_QSPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SPI_FLASH_BAR
+#define CONFIG_SYS_FSL_QSPI_AHB
+#define CONFIG_SF_DEFAULT_BUS           0
+#define CONFIG_SF_DEFAULT_CS            0
+#define CONFIG_SF_DEFAULT_SPEED         40000000
+#define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
+#ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2
+#define FSL_QSPI_FLASH_NUM              2
+#define FSL_QSPI_FLASH_SIZE             SZ_32M
+#else
+#define FSL_QSPI_FLASH_NUM              1
+#define FSL_QSPI_FLASH_SIZE             SZ_64M
+#endif
+#define QSPI0_BASE_ADDR                 0x410A5000
+#define QSPI0_AMBA_BASE                 0xC0000000
+#define CONFIG_QSPI_BASE	QSPI0_BASE_ADDR
+#define CONFIG_QSPI_MEMMAP_BASE	QSPI0_AMBA_BASE
+#endif
+
+#endif	/* __CONFIG_H */