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| author | Fugang Duan <fugang.duan@nxp.com> | 2017-07-11 11:21:32 +0800 |
|---|---|---|
| committer | Fugang Duan <fugang.duan@nxp.com> | 2017-07-12 17:35:20 +0800 |
| commit | 721193c18f248faa1c892cc64fc656b21b7320b8 (patch) | |
| tree | 1932166bde5da5f22e4a1002645b793cd94402e1 | |
| parent | d7a3a0d51912e81f6b81132c718fcba57463229b (diff) | |
| download | u-boot-imx-721193c18f248faa1c892cc64fc656b21b7320b8.zip u-boot-imx-721193c18f248faa1c892cc64fc656b21b7320b8.tar.gz u-boot-imx-721193c18f248faa1c892cc64fc656b21b7320b8.tar.bz2 | |
MLK-15341 mx6qpsabresd: add PHY AR8031 hw reset
Currently mx6qpsabresd board file only add PHY AR8031 gpio reset
in non-DM driver, then net DM driver PHY cannot work after stress
reboot test. So also add gpio reset for DM driver.
RGMII and PHY work at VDDIO 1.8V has better timing and to align
the IO voltage with kernel, also set the IO voltage to 1.8V.
Since i.MX6QP tx_clk can loop from SOC internal, no need to set
PHY output 125Mhz clock that can save power.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | board/freescale/mx6sabresd/mx6sabresd.c | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 2a09e2f..9f60943 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -111,10 +111,8 @@ static iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), }; -static void setup_iomux_enet(void) +static void fec_phy_reset(void) { - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - /* Reset AR8031 PHY */ gpio_request(IMX_GPIO_NR(1, 25), "ENET PHY Reset"); gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); @@ -123,6 +121,12 @@ static void setup_iomux_enet(void) udelay(100); } +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + fec_phy_reset(); +} + static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -459,14 +463,20 @@ static int ar8031_phy_fixup(struct phy_device *phydev) unsigned short val; /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + if (!is_mx6dqp()) { + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xffe3; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + } - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + /* set the IO voltage to 1.8v */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); /* introduce tx clock delay */ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); @@ -817,6 +827,8 @@ static void setup_fec(void) if (ret) printf("Error fec anatop clock settings!\n"); } + + fec_phy_reset(); } int board_eth_init(bd_t *bis) |