igep0046: DL,2G

SPL support: Falcon by default
Falcon support: Ramdisk configurable in defconfig

Signed-off-by: Jose Miguel Sanchez Sanabria <jsanabria@iseebcn.com>

5 files changed, 462 insertions, 9 deletions

diff --git a/board/isee/igep0046/Kconfig b/board/isee/igep0046/Kconfig
index 5ca6e3a..c932c91 100644
--- a/board/isee/igep0046/Kconfig
+++ b/board/isee/igep0046/Kconfig
@@ -21,4 +21,14 @@ config BASE0040
 
 endchoice
 
+config WITH_SPL_SUPPORT
+	bool "Build i.MX6 with SPL support"
+	select SUPPORT_SPL
+	help
+	  Builds IGEP i.MX6 boards with SPL support
+
+config FALCON_RAMDISK
+	bool "FALCON mode with INITRD RAMDISK support"
+	help
+	  Builds IGEP i.MX6 boards FALCON mode with INITRD RAMDISK support
 endif
diff --git a/board/isee/igep0046/igep0046.c b/board/isee/igep0046/igep0046.c
index ce11717..85c983e 100644
--- a/board/isee/igep0046/igep0046.c
+++ b/board/isee/igep0046/igep0046.c
@@ -13,6 +13,7 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
+#include <asm/arch/mx6-ddr.h>
 #include <linux/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/mxc_i2c.h>
@@ -26,7 +27,6 @@
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-mx6/sys_proto.h>
-#include <asm/arch/mx6-ddr.h>
 #include <i2c.h>
 #include <asm/io.h>
 #include <power/pmic.h>
@@ -35,6 +35,7 @@
 #include "igep0046_eeprom.h"
 #include "../common/igep_common.h"
 #include <usb.h>
+#include <mmc.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -85,13 +86,18 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PCB_REV_C	3
 #define PCB_REV_D10	4
 
-
 int dram_init(void)
 {
 	gd->ram_size = imx_ddr_size();
 	return 0;
 }
 
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = imx_ddr_size();
+}
+
 /* UART MUX */
 static iomux_v3_cfg_t const uart1_pads[] =
 {
@@ -619,4 +625,389 @@ void reset_phy(void)
 	/* configure and initialize */
 	mv_phy_88e1510_init("FEC");
 }
-#endif /* CONFIG_RESET_PHY_R */
\ No newline at end of file
+#endif /* CONFIG_RESET_PHY_R */
+
+/* Add SPL Support if we want to build u-boot with SPL for i.MX6 */
+
+#ifdef CONFIG_SPL_BUILD
+#include <spl.h>
+#include <libfdt.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
+#include "pfuze.h"
+
+#define IMX6DQ_DRIVE_STRENGTH		0x30
+#define IMX6SDL_DRIVE_STRENGTH		0x28
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+
+#ifdef CONFIG_MX6Q
+static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+static struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* DDR 64bit 2GB */
+static struct mx6_ddr_sysinfo mem_q = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+static struct mx6_mmdc_calibration mx6q_2g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x00530056,
+	.p0_mpwldectrl1 = 0x00440053,
+	.p1_mpwldectrl0 = 0x002B002B,
+	.p1_mpwldectrl1 = 0x0028003F,
+	.p0_mpdgctrl0 = 0x021C021C,
+	.p0_mpdgctrl1 = 0x02140214,
+	.p1_mpdgctrl0 = 0x0178017C,
+	.p1_mpdgctrl1 = 0x016C0170,
+	.p0_mprddlctl = 0x46484C48,
+	.p1_mprddlctl = 0x42424842,
+	.p0_mpwrdlctl = 0x3434302E,
+	.p1_mpwrdlctl = 0x3A303830,
+};
+#endif
+
+static struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+	.dram_sdclk_0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdclk_1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_cas = IMX6DQ_DRIVE_STRENGTH,
+	.dram_ras = IMX6DQ_DRIVE_STRENGTH,
+	.dram_reset = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdcke1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdba2 = 0x00000000,
+	.dram_sdodt0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdodt1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_sdqs7 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm0 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm1 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm2 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm3 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm4 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm5 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm6 = IMX6DQ_DRIVE_STRENGTH,
+	.dram_dqm7 = IMX6DQ_DRIVE_STRENGTH,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+	.grp_ddr_type = 0x000c0000,
+	.grp_ddrmode_ctl = 0x00020000,
+	.grp_ddrpke = 0x00000000,
+	.grp_addds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ctlds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_ddrmode = 0x00020000,
+	.grp_b0ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b1ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b2ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b3ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b4ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b5ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b6ds = IMX6DQ_DRIVE_STRENGTH,
+	.grp_b7ds = IMX6DQ_DRIVE_STRENGTH,
+};
+
+static struct mx6_ddr_sysinfo mem_dl = {
+	.dsize		= 2, /* MMDCx_MDCTL */
+	.cs1_mirror	= 0, /* MMDCx_MDMISC */
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32, /* MMDCx_MDCTL */
+	.ncs		= 1, /* MMDCx_MDCTL */
+	.bi_on		= 1, /* MMDCx_MDMISC */
+	.rtt_nom	= 1, /* MMDCx_MPODTCTRL */
+	.rtt_wr		= 0, /* - */
+	.ralat		= 5, /* MMDCx_MDMISC */
+	.walat		= 0, /* MMDCx_MDMISC */
+	.mif3_mode	= 3, /* MMDCx_MDMISC */
+	.rst_to_cke	= 0x23, /* MMDCx_MDOR */
+	.sde_to_rst	= 0x10, /* MMDCx_MDOR */
+};
+
+static struct mx6_ddr_sysinfo mem_s = {
+	.dsize		= 2,
+	.cs1_mirror	= 0,
+	/* config for full 4GB range so that get_mem_size() works */
+	.cs_density	= 32,
+	.ncs		= 1,
+	.bi_on		= 1,
+	.rtt_nom	= 1,
+	.rtt_wr		= 0,
+	.ralat		= 5,
+	.walat		= 0,
+	.mif3_mode	= 3,
+	.rst_to_cke	= 0x23,
+	.sde_to_rst	= 0x10,
+};
+
+/* K484G1646D-8MK0 (4Gb density) */
+static struct mx6_ddr3_cfg k484g1646d_8mk0 = {
+	.mem_speed = 1600,
+	.density = 4,
+	.width = 16,
+	.banks = 8,
+	.rowaddr = 15,
+	.coladdr = 10,
+	.pagesz = 2,
+	.trcd = 1375,
+	.trcmin = 4875,
+	.trasmin = 3500,
+};
+
+static struct mx6_mmdc_calibration mx6dl_2g_mmdc_calib = {
+	.p0_mpwldectrl0 = 0x00530056,
+	.p0_mpwldectrl1 = 0x00440053,
+	.p1_mpwldectrl0 = 0x002B002B,
+	.p1_mpwldectrl1 = 0x0028003F,
+	.p0_mpdgctrl0 = 0x021C021C,
+	.p0_mpdgctrl1 = 0x02140214,
+	.p1_mpdgctrl0 = 0x0178017C,
+	.p1_mpdgctrl1 = 0x016C0170,
+	.p0_mprddlctl = 0x46484C48,
+	.p1_mprddlctl = 0x42424842,
+	.p0_mpwrdlctl = 0x3434302E,
+	.p1_mpwrdlctl = 0x3A303830,
+};
+
+static void spl_dram_init(void)
+{
+
+/* TO DO: IMPLEMENT CASE FOR EACH MEMORY DEVICE AND MEMORY DENSITY CONFIGURATION (1,2,4 GB) */
+
+	if (is_cpu_type(MXC_CPU_MX6SOLO)) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_s, &mx6dl_2g_mmdc_calib, &k484g1646d_8mk0);
+	} else if (is_cpu_type(MXC_CPU_MX6DL)) {
+		mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
+		mx6_dram_cfg(&mem_dl, &mx6dl_2g_mmdc_calib, &k484g1646d_8mk0);
+	}
+#ifdef CONFIG_MX6Q
+	else if (is_cpu_type(MXC_CPU_MX6Q)) {
+		mx6dq_dram_iocfg(64, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
+		mx6_dram_cfg(&mem_q, &mx6q_2g_mmdc_calib, &k484g1646d_8mk0);
+	}
+#endif
+	udelay(100);
+}
+
+static void ccgr_init(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	writel(0x00C03F3F, &ccm->CCGR0);
+	writel(0x0030FC03, &ccm->CCGR1);
+	writel(0x0FFFC000, &ccm->CCGR2);
+	writel(0x3FF00000, &ccm->CCGR3);
+	writel(0x00FFF300, &ccm->CCGR4);
+	writel(0x0F0000C3, &ccm->CCGR5);
+	writel(0x000003FF, &ccm->CCGR6);
+}
+
+static void gpr_init(void)
+{
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
+
+	/* enable AXI cache for VDOA/VPU/IPU */
+	writel(0xF00000CF, &iomux->gpr[4]);
+	if (is_mx6dqp()) {
+		/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	} else {
+		/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+		writel(0x007F007F, &iomux->gpr[6]);
+		writel(0x007F007F, &iomux->gpr[7]);
+	}
+}
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+
+	/* setup AIPS and disable watchdog */
+	arch_cpu_init();
+
+	/* setup clock gating */
+	ccgr_init();
+
+	/* setup general purpose register */
+	gpr_init();
+
+	/* iomux and setup of UART and leds */
+	board_early_init_f();
+
+	/* setup GP timer */
+	timer_init();
+
+	/* Silent Console */
+	gd->flags |= GD_FLG_SILENT;
+	/* UART clocks enabled and gd valid - init serial console */
+	preloader_console_init();
+
+	/* DDR initialization */
+	spl_dram_init();
+
+	/* Get RAM size */
+	dram_init();
+
+	/* Initialize SDRAM banks - fdt_fixup*/
+	dram_init_banksize();
+
+	/* Clear the BSS. */
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	
+	/* load/boot image from boot device */
+	board_init_r(NULL, 0);
+}
+
+/* called from board_init_r after gd setup if CONFIG_SPL_BOARD_INIT defined */
+/* its our chance to print info about boot device */
+void spl_board_init(void)
+{
+	/* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 */
+	u32 boot_device = spl_boot_device();
+
+	switch (boot_device) {
+	case BOOT_DEVICE_MMC1:
+		puts("Booting from MMC\n");
+		break;
+	case BOOT_DEVICE_NAND:
+		puts("Booting from NAND\n");
+		break;
+	case BOOT_DEVICE_SATA:
+		puts("Booting from SATA\n");
+		break;
+	default:
+		puts("Unknown boot device\n");
+	}
+	
+	/* Minimal init sequence for pmic setup of igep imx6 boards */
+	#ifdef CONFIG_BASE0040
+	reset_audio();
+	#endif
+
+	#ifdef CONFIG_SYS_I2C
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	mdelay(1);
+	#endif
+
+	/* PMIC init */
+	power_init_board();
+}
+
+#ifdef CONFIG_SPL_OS_BOOT
+/* return 1 if we wish to boot to uboot vs os (falcon mode) */
+int spl_start_uboot(void)
+{
+	return 0;
+}
+
+void spl_board_prepare_for_linux(void)
+{
+	/* Fill here igep i.MX6 specific code to set up board just before
+	Jumping to Linux in SPL Falcon Mode */
+
+#ifdef CONFIG_FALCON_RAMDISK
+
+	#define CONFIG_RAMDISK_START	0x5000
+	#define CONFIG_RAMDISK_SIZE		22 * 1024 * 1024
+	#define CONFIG_RAMDISK_ARG_DDR	0x14000000
+	#define CONFIG_RAMDISK_MMC_DEV 	0
+
+	u32 initrd_size_sectors;
+	ulong start;
+	ulong size;
+	int dev;
+	struct mmc *mmc;
+
+	/* We need to re-fill mmc structure for blk_dread to work with mmc */
+	dev = CONFIG_RAMDISK_MMC_DEV;
+	mmc = find_mmc_device(dev);
+	if (!mmc) {
+		puts("error MMC init\n");
+	}
+
+	mmc_init(mmc);
+
+	/* We expect initrd.img in offset RAMDISK_ARG_DDR of device x */
+	start = CONFIG_RAMDISK_START;
+	/* We exect initrd.img to be size of RAMDISK_SIZE */
+	size = CONFIG_RAMDISK_SIZE;
+
+	/* convert size to sectors - round up */
+	initrd_size_sectors = (size / 512);
+
+	/* Load initrd.img from RAW MMC starting at start with size size into 0x14000000 ADDR */
+	blk_dread(mmc_get_blk_desc(mmc), start, initrd_size_sectors,
+			  (void *)CONFIG_RAMDISK_ARG_DDR);
+
+#endif
+}
+
+#endif
+#endif
diff --git a/configs/igep0046_imx6dl_2G_defconfig b/configs/igep0046_imx6dl_2G_defconfig
index 8af18e0..7e299d5 100644
--- a/configs/igep0046_imx6dl_2G_defconfig
+++ b/configs/igep0046_imx6dl_2G_defconfig
@@ -6,10 +6,11 @@ CONFIG_SYS_MALLOC_F_LEN=0x400
 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/isee/igep0046/mx6dl_igep0046_4x512_nt.cfg,MX6DL"
 CONFIG_BOOTDELAY=3
 CONFIG_OF_LIBFDT=y
+CONFIG_CMD_FDT=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_SPLASH_SCREEN=n
 CONFIG_DEFAULT_FDT_FILE="imx6dl-igep-base0040rd102.dtb"
 CONFIG_BASE0040=y
-CONFIG_HUSH_PARSER=y
\ No newline at end of file
+CONFIG_HUSH_PARSER=y
diff --git a/configs/igep0046_imx6dl_2G_spl_defconfig b/configs/igep0046_imx6dl_2G_spl_defconfig
new file mode 100644
index 0000000..de9cb94
--- /dev/null
+++ b/configs/igep0046_imx6dl_2G_spl_defconfig
@@ -0,0 +1,36 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MX6=y
+CONFIG_TARGET_IGEP0046=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_BOOTDELAY=3
+CONFIG_OF_LIBFDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+CONFIG_SPLASH_SCREEN=n
+CONFIG_DEFAULT_FDT_FILE="imx6dl-igep-base0040rd102.dtb"
+CONFIG_BASE0040=y
+CONFIG_HUSH_PARSER=y
+
+# Falcon Support
+
+CONFIG_WITH_SPL_SUPPORT=y
+CONFIG_FALCON_RAMDISK=y
+CONFIG_SUPPORT_SPL=y
+CONFIG_SPL=y
+CONFIG_SPL_BUILD=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SPL_I2C_SUPPORT=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_DMA_SUPPORT=n
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_WATCHDOG_SUPPORT=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/imx-common/spl_sd.cfg,SPL,MX6DL"
+CONFIG_SPL_EXT_SUPPORT=y
+CONFIG_SPL_POWER_SUPPORT=y
diff --git a/include/configs/igep0046.h b/include/configs/igep0046.h
index 00a64ae..4f963e0 100644
--- a/include/configs/igep0046.h
+++ b/include/configs/igep0046.h
@@ -13,6 +13,24 @@
 
 #include "mx6_common.h"	
 
+/* Falcon Mode */
+#ifdef CONFIG_SPL
+#include "imx6_spl.h"
+
+#define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
+#define CONFIG_SPL_FS_LOAD_KERNEL_NAME	"uImage"
+#define CONFIG_CMD_SPL
+#define CONFIG_SPL_BOARD_INIT
+
+#define CONFIG_SYS_SPL_ARGS_ADDR       0x18000000
+#define CONFIG_CMD_SPL_WRITE_SIZE      (128 * SZ_1K)
+
+/* Falcon Mode - RAW MMC support: args@1MB kernel@2MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
+#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR        0x1000  /* 2MB */
+#endif
+
 /* CPU */
 #define CONFIG_IMX_THERMAL
 
@@ -45,9 +63,10 @@
 
 /* Begin and End Address of simple memory test */
 #define CONFIG_SYS_MEMTEST_START       0x10000000
-#define CONFIG_SYS_MEMTEST_END         0x10010000
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
 
+
 /* Miscellaneous configurable options */
 #define CONFIG_AUTOBOOT_KEYED
 #define CONFIG_AUTOBOOT_PROMPT "Press ESC to abort autoboot in %d seconds\n"
@@ -55,8 +74,6 @@
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_AUTO_COMPLETE
-#define CONFIG_LOADADDR                0x12000000
-#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_STACKSIZE               (128 * 1024)
 
@@ -69,7 +86,6 @@
 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 #define CONFIG_SYS_I2C_SPEED		100000
 
-
 /* PMIC Configs */
 #define CONFIG_POWER
 #define CONFIG_POWER_I2C
@@ -89,7 +105,6 @@
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #define CONFIG_DOS_PARTITION
 
-
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_FAT_WRITE