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| author | Ye Li <ye.li@nxp.com> | 2017-04-20 10:16:24 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-04-20 13:31:41 +0800 |
| commit | 2c101b1d4cccee4eb711110ea19cf92014cf56d8 (patch) | |
| tree | 81544611a2729250a03db681a92d27b9ef6e8080 | |
| parent | f04444fa8a1c8c99fad5d8781324cff27892b9b6 (diff) | |
| download | u-boot-imx-2c101b1d4cccee4eb711110ea19cf92014cf56d8.zip u-boot-imx-2c101b1d4cccee4eb711110ea19cf92014cf56d8.tar.gz u-boot-imx-2c101b1d4cccee4eb711110ea19cf92014cf56d8.tar.bz2 | |
MLK-14707 fsl_esdhc: Fix eMMC 1.8v setting issue
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.
Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f01ebfdaa57b4c74ede32a6a40cf9cf9184ce049)
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index c0e64ee..9bfd3a4 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -652,7 +652,10 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->clktunectrlstatus, 0x0); /* Put VEND_SPEC to default value */ - esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); + if (priv->vs18_enable) + esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | ESDHC_VENDORSPEC_VSELECT)); + else + esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); /* Disable DLL_CTRL delay line */ esdhc_write32(®s->dllctrl, 0x0); @@ -681,9 +684,6 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); - if (priv->vs18_enable) - esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); - return 0; } |