ppc4xx: remove OCRTC board

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

11 files changed, 1 insertions, 632 deletions

diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index cab8f25..ea4227e 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -125,9 +125,6 @@ config TARGET_CPCI405AB
 config TARGET_CPCI405DT
 	bool "Support CPCI405DT"
 
-config TARGET_OCRTC
-	bool "Support OCRTC"
-
 config TARGET_PCI405
 	bool "Support PCI405"
 
@@ -229,7 +226,6 @@ source "board/csb472/Kconfig"
 source "board/dave/PPChameleonEVB/Kconfig"
 source "board/esd/cpci2dp/Kconfig"
 source "board/esd/cpci405/Kconfig"
-source "board/esd/ocrtc/Kconfig"
 source "board/esd/pci405/Kconfig"
 source "board/esd/plu405/Kconfig"
 source "board/esd/pmc405/Kconfig"
diff --git a/board/esd/ocrtc/Kconfig b/board/esd/ocrtc/Kconfig
deleted file mode 100644
index 44b402d..0000000
--- a/board/esd/ocrtc/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OCRTC
-
-config SYS_BOARD
-	default "ocrtc"
-
-config SYS_VENDOR
-	default "esd"
-
-config SYS_CONFIG_NAME
-	default "OCRTC"
-
-endif
diff --git a/board/esd/ocrtc/MAINTAINERS b/board/esd/ocrtc/MAINTAINERS
deleted file mode 100644
index 85c1a12..0000000
--- a/board/esd/ocrtc/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OCRTC BOARD
-M:	Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S:	Maintained
-F:	board/esd/ocrtc/
-F:	include/configs/OCRTC.h
-F:	configs/OCRTC_defconfig
diff --git a/board/esd/ocrtc/Makefile b/board/esd/ocrtc/Makefile
deleted file mode 100644
index 44b7d5d..0000000
--- a/board/esd/ocrtc/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	= ocrtc.o flash.o ../common/misc.o cmd_ocrtc.o
diff --git a/board/esd/ocrtc/cmd_ocrtc.c b/board/esd/ocrtc/cmd_ocrtc.c
deleted file mode 100644
index 6dcbd8b..0000000
--- a/board/esd/ocrtc/cmd_ocrtc.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * (C) Copyright 2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <pci.h>
-#include <pci_ids.h>
-#include <asm/4xx_pci.h>
-
-
-#if defined(CONFIG_CMD_BSP)
-
-/*
- * Set device number on pci board
- */
-int do_setdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	int idx = 1;	  /* start at 1 (skip device 0) */
-	pci_dev_t bdf = 0;
-	u32 addr;
-
-	while (bdf >= 0) {
-		if ((bdf = pci_find_device(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_405GP, idx++)) < 0) {
-			break;
-		}
-		printf("Found device nr %d at %x!\n", idx-1, bdf);
-		pci_read_config_dword(bdf, PCI_BASE_ADDRESS_1, &addr);
-		addr &= ~0xf;
-		*(u32 *)addr = (bdf & 0x0000f800) >> 11;
-		printf("Wrote %x at %x!\n", (bdf & 0x0000f800) >> 11, addr);
-	}
-
-	return 0;
-}
-U_BOOT_CMD(
-	setdevice,	1,	1,	do_setdevice,
-	"Set device number on pci adapter boards",
-	""
-);
-
-
-/*
- * Get device number on pci board
- */
-int do_getdevice(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	u32 device;
-	char str[32];
-
-	device = *(u32 *)0x0;
-	device = 0x16 - device;      /* calculate vxworks bp slot id */
-	sprintf(str, "%d", device);
-	setenv("slot", str);
-	printf("Variabel slot set to %x\n", device);
-
-	return 0;
-}
-U_BOOT_CMD(
-	getdevice,	1,	1,	do_getdevice,
-	"Get device number and set slot env variable",
-	""
-);
-
-#endif
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
deleted file mode 100644
index 279746e..0000000
--- a/board/esd/ocrtc/flash.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
-	unsigned long size_b0, size_b1;
-	int i;
-	uint pbcr;
-	unsigned long base_b0, base_b1;
-	int size_val = 0;
-
-	/* Init: no FLASHes known */
-	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
-		flash_info[i].flash_id = FLASH_UNKNOWN;
-	}
-
-	/* Static FLASH Bank configuration here - FIXME XXX */
-
-	base_b0 = FLASH_BASE0_PRELIM;
-	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
-	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
-		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
-			size_b0, size_b0 << 20);
-	}
-
-	base_b1 = FLASH_BASE1_PRELIM;
-	size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
-	/* Re-do sizing to get full correct info */
-
-	if (size_b1) {
-		mtdcr (EBC0_CFGADDR, PB0CR);
-		pbcr = mfdcr (EBC0_CFGDATA);
-		mtdcr (EBC0_CFGADDR, PB0CR);
-		base_b1 = -size_b1;
-		switch (size_b1) {
-		case 1 << 20:
-			size_val = 0;
-			break;
-		case 2 << 20:
-			size_val = 1;
-			break;
-		case 4 << 20:
-			size_val = 2;
-			break;
-		case 8 << 20:
-			size_val = 3;
-			break;
-		case 16 << 20:
-			size_val = 4;
-			break;
-		}
-		pbcr = (pbcr & 0x0001ffff) | base_b1 | (size_val << 17);
-		mtdcr (EBC0_CFGDATA, pbcr);
-		/*          printf("PB1CR = %x\n", pbcr); */
-	}
-
-	if (size_b0) {
-		mtdcr (EBC0_CFGADDR, PB1CR);
-		pbcr = mfdcr (EBC0_CFGDATA);
-		mtdcr (EBC0_CFGADDR, PB1CR);
-		base_b0 = base_b1 - size_b0;
-		switch (size_b1) {
-		case 1 << 20:
-			size_val = 0;
-			break;
-		case 2 << 20:
-			size_val = 1;
-			break;
-		case 4 << 20:
-			size_val = 2;
-			break;
-		case 8 << 20:
-			size_val = 3;
-			break;
-		case 16 << 20:
-			size_val = 4;
-			break;
-		}
-		pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
-		mtdcr (EBC0_CFGDATA, pbcr);
-		/*            printf("PB0CR = %x\n", pbcr); */
-	}
-
-	size_b0 = flash_get_size ((vu_long *) base_b0, &flash_info[0]);
-
-	flash_get_offsets (base_b0, &flash_info[0]);
-
-	/* monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-			base_b0 + size_b0 - monitor_flash_len,
-			base_b0 + size_b0 - 1, &flash_info[0]);
-
-	if (size_b1) {
-		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size ((vu_long *) base_b1, &flash_info[1]);
-
-		flash_get_offsets (base_b1, &flash_info[1]);
-
-		/* monitor protection ON by default */
-		flash_protect (FLAG_PROTECT_SET,
-				base_b1 + size_b1 - monitor_flash_len,
-				base_b1 + size_b1 - 1, &flash_info[1]);
-		/* monitor protection OFF by default (one is enough) */
-		flash_protect (FLAG_PROTECT_CLEAR,
-				base_b0 + size_b0 - monitor_flash_len,
-				base_b0 + size_b0 - 1, &flash_info[0]);
-	} else {
-		flash_info[1].flash_id = FLASH_UNKNOWN;
-		flash_info[1].sector_count = -1;
-	}
-
-	flash_info[0].size = size_b0;
-	flash_info[1].size = size_b1;
-
-	return (size_b0 + size_b1);
-}
diff --git a/board/esd/ocrtc/ocrtc.c b/board/esd/ocrtc/ocrtc.c
deleted file mode 100644
index b815961..0000000
--- a/board/esd/ocrtc/ocrtc.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include "ocrtc.h"
-#include <asm/processor.h>
-#include <i2c.h>
-#include <command.h>
-
-
-extern void lxt971_no_sleep(void);
-
-
-int board_early_init_f (void)
-{
-	/*
-	 * IRQ 0-15  405GP internally generated; active high; level sensitive
-	 * IRQ 16    405GP internally generated; active low; level sensitive
-	 * IRQ 17-24 RESERVED
-	 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
-	 * IRQ 26 (EXT IRQ 1) CAN1; active low; level sensitive
-	 * IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
-	 * IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
-	 * IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
-	 * IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
-	 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
-	 */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-	mtdcr (UIC0ER, 0x00000000);	/* disable all ints */
-	mtdcr (UIC0CR, 0x00000000);	/* set all to be non-critical */
-	mtdcr (UIC0PR, 0xFFFFFF81);	/* set int polarities */
-	mtdcr (UIC0TR, 0x10000000);	/* set int trigger levels */
-	mtdcr (UIC0VCR, 0x00000001);	/* set vect base=0,INT0 highest priority */
-	mtdcr (UIC0SR, 0xFFFFFFFF);	/* clear all ints */
-
-	/*
-	 * EBC Configuration Register: clear EBTC -> high-Z ebc signals between
-	 * transfers, set device-paced timeout to 256 cycles
-	 */
-	mtebc (EBC0_CFG, 0x20400000);
-
-	return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
-	char str[64];
-	int i = getenv_f("serial#", str, sizeof (str));
-
-	puts ("Board: ");
-
-	if (i == -1) {
-#ifdef CONFIG_OCRTC
-		puts ("### No HW ID - assuming OCRTC");
-#endif
-#ifdef CONFIG_ORSG
-		puts ("### No HW ID - assuming ORSG");
-#endif
-	} else {
-		puts (str);
-	}
-
-	putc ('\n');
-
-	/*
-	 * Disable sleep mode in LXT971
-	 */
-	lxt971_no_sleep();
-
-	return (0);
-}
diff --git a/board/esd/ocrtc/ocrtc.h b/board/esd/ocrtc/ocrtc.h
deleted file mode 100644
index 029e27e..0000000
--- a/board/esd/ocrtc/ocrtc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/****************************************************************************
- * FLASH Memory Map as used by TQ Monitor:
- *
- *                          Start Address    Length
- * +-----------------------+ 0x4000_0000     Start of Flash -----------------
- * | MON8xx code           | 0x4000_0100     Reset Vector
- * +-----------------------+ 0x400?_????
- * | (unused)              |
- * +-----------------------+ 0x4001_FF00
- * | Ethernet Addresses    |                 0x78
- * +-----------------------+ 0x4001_FF78
- * | (Reserved for MON8xx) |                 0x44
- * +-----------------------+ 0x4001_FFBC
- * | Lock Address          |                 0x04
- * +-----------------------+ 0x4001_FFC0                     ^
- * | Hardware Information  |                 0x40            | MON8xx
- * +=======================+ 0x4002_0000 (sector border)    -----------------
- * | Autostart Header      |                                 | Applications
- * | ...                   |                                 v
- *
- *****************************************************************************/
diff --git a/configs/OCRTC_defconfig b/configs/OCRTC_defconfig
deleted file mode 100644
index f2fd0c5..0000000
--- a/configs/OCRTC_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_OCRTC=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index d8bb3aa..0b449d1 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
 
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+OCRTC            ppc4xx      405gpr         -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 HUB405           ppc4xx      405ep          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 HH405            ppc4xx      405ep          -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
 DU440            ppc4xx      440epx         -           -           Matthias Fuchs <matthias.fuchs@esd.eu>
diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
deleted file mode 100644
index 4680afe..0000000
--- a/include/configs/OCRTC.h
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
-#define CONFIG_OCRTC		1	/* ...on a OCRTC board		*/
-
-#define	CONFIG_SYS_TEXT_BASE	0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
-
-#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll	*/
-
-#define CONFIG_BAUDRATE		9600
-#define CONFIG_BOOTDELAY	3	/* autoboot after 3 seconds	*/
-
-#undef	CONFIG_BOOTARGS
-#define CONFIG_BOOTCOMMAND "go fff00100"
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_PHY_ADDR		0	/* PHY address			*/
-#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_BSP
-#define CONFIG_CMD_EEPROM
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET	1	/* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
-#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
-
-#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
-
-#undef	CONFIG_SYS_EXT_SERIAL_CLOCK	       /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD	    691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
-	 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR	0x100000	/* default load address */
-#define CONFIG_SYS_EXTBDINFO	1		/* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0		/* configure as pci adapter	*/
-#define PCI_HOST_FORCE	1		/* configure as pci host	*/
-#define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
-
-#define CONFIG_PCI			/* include pci support		*/
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_PCI_HOST PCI_HOST_AUTO	/* select pci host function	*/
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-					/* resource configuration	*/
-
-#define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
-
-#define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
-#define CONFIG_SYS_PCI_CLASSCODE	0x0b20	/* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA	0x00000000	/* point to sdram		*/
-#define CONFIG_SYS_PCI_PTM1MS	0xfc000001	/* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000	/* Host: use this pci address	*/
-#define CONFIG_SYS_PCI_PTM2LA	0xffc00000	/* point to flash		*/
-#define CONFIG_SYS_PCI_PTM2MS	0xffc00001	/* 4MB, enable			*/
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000	/* Host: use this pci address	*/
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BASE		0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN		(192 * 1024)	/* Reserve 192 kB for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
-
-#define CONFIG_SYS_FLASH_WORD_SIZE	unsigned short	/* flash word size (width)	*/
-#define CONFIG_SYS_FLASH_ADDR0		0x5555	/* 1st address for flash config cycles	*/
-#define CONFIG_SYS_FLASH_ADDR1		0x2AAA	/* 2nd address for flash config cycles	*/
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
-
-#if 0 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM	1	/* use NVRAM for environment vars	*/
-#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0200000		/* NVRAM base address	*/
-#define CONFIG_SYS_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
-#define CONFIG_ENV_SIZE		0x1000		/* Size of Environment vars	*/
-#define CONFIG_ENV_ADDR		\
-	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env	*/
-#define CONFIG_SYS_NVRAM_VXWORKS_OFFS	0x6900		/* Offset for VxWorks eth-addr	*/
-
-#else /* Use EEPROM for environment variables */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET		0x000	/* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		0x300	/* 768 bytes may be used for env vars */
-				   /* total size of a CAT24WC08 is 1024 bytes */
-#endif
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC08) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM CAT28WC08		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* Bytes of address		*/
-/* mask of address bits that overflow into the "EEPROM chip address"	*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4	/* The Catalyst CAT24WC08 has	*/
-					/* 16 byte page write mode using*/
-					/* last 4 bits of the address	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM	0xFF800000	/* FLASH bank #0	*/
-#define FLASH_BASE1_PRELIM	0xFFC00000	/* FLASH bank #1	*/
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0) initialization					*/
-#define CONFIG_SYS_EBC_PB0AP		0x92015480
-#define CONFIG_SYS_EBC_PB0CR		0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1) initialization					*/
-#define CONFIG_SYS_EBC_PB1AP		0x92015480
-#define CONFIG_SYS_EBC_PB1CR		0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 2 (PLD - FPGA-boot) initialization				*/
-#define CONFIG_SYS_EBC_PB2AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB2CR		0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 3 (PLD - OSL) initialization					*/
-#define CONFIG_SYS_EBC_PB3AP		0x02015480  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB3CR		0xF0118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit	*/
-
-/* Memory Bank 4 (Spartan2 1) initialization					*/
-#define CONFIG_SYS_EBC_PB4AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB4CR		0xF209C000  /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 5 (Spartan2 2) initialization					*/
-#define CONFIG_SYS_EBC_PB5AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB5CR		0xF309C000  /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/
-
-/* Memory Bank 6 (Virtex 1) initialization					*/
-#define CONFIG_SYS_EBC_PB6AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB6CR		0xF409A000  /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/
-
-/* Memory Bank 7 (Virtex 2) initialization					*/
-#define CONFIG_SYS_EBC_PB7AP		0x02015580  /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */
-					    /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/
-#define CONFIG_SYS_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
-
-
-#define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM	  1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
-
-#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
-#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/
-#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#endif	/* __CONFIG_H */