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| author | Ye Li <ye.li@nxp.com> | 2016-10-11 15:06:09 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-10-12 16:00:00 +0800 |
| commit | be0b2d9cb2969725d0231bc9836a3e2c39f84dee (patch) | |
| tree | 75c6b0be4a55e009957c9634c212e56fef3718bd | |
| parent | 92946cba62d23e6ace547a90a0debb1916fa0add (diff) | |
| download | u-boot-imx-be0b2d9cb2969725d0231bc9836a3e2c39f84dee.zip u-boot-imx-be0b2d9cb2969725d0231bc9836a3e2c39f84dee.tar.gz u-boot-imx-be0b2d9cb2969725d0231bc9836a3e2c39f84dee.tar.bz2 | |
MLK-13331 mx6sll_arm2: Output WDOG_B signal to reset PMIC
Since the LPDDR2/3 does not have reset pin, to keep safe reset, we need
to use WDOG_B to reset PMIC. Add pinmux and relevant settings.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | board/freescale/mx6sll_arm2/mx6sll_arm2.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/board/freescale/mx6sll_arm2/mx6sll_arm2.c b/board/freescale/mx6sll_arm2/mx6sll_arm2.c index a8f40da..e7b8f5a 100644 --- a/board/freescale/mx6sll_arm2/mx6sll_arm2.c +++ b/board/freescale/mx6sll_arm2/mx6sll_arm2.c @@ -105,6 +105,10 @@ int dram_init(void) return 0; } +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_WDOG_B__WDOG1_B | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static iomux_v3_cfg_t const led_pads[] = { MX6_PAD_EPDC_VCOM1__GPIO2_IO04 | MUX_PAD_CTRL(UART_PAD_CTRL), }; @@ -503,6 +507,10 @@ int board_late_init(void) board_late_mmc_env_init(); #endif + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR); + return 0; } |