diff options
| author | Ye Li <ye.li@nxp.com> | 2017-01-23 16:39:11 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2017-01-23 17:59:42 +0800 |
| commit | aa3e2f4dc91bdc2df22f208bad0cd24414fe8a63 (patch) | |
| tree | d81897d9b38f3d9b8c28620c6fe2951911425a4a | |
| parent | 0b217456375bace3fbe9a72c7e92a46dc1907277 (diff) | |
| download | u-boot-imx-aa3e2f4dc91bdc2df22f208bad0cd24414fe8a63.zip u-boot-imx-aa3e2f4dc91bdc2df22f208bad0cd24414fe8a63.tar.gz u-boot-imx-aa3e2f4dc91bdc2df22f208bad0cd24414fe8a63.tar.bz2 | |
MLK-13816 mx7ulp_evk/arm: Fix pad setting issue for OTG_ID
The EVK and ARM2 board uses GPIOs for OTD_ID and USB_PWR. The PAD setting for
OTG_ID is wrong, which should not enable output (OBE). Otherwise the device
mode can't be recognized. Corret the pad settings for them.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | board/freescale/mx7ulp_arm2/mx7ulp_arm2.c | 12 | ||||
| -rw-r--r-- | board/freescale/mx7ulp_evk/mx7ulp_evk.c | 8 |
2 files changed, 13 insertions, 7 deletions
diff --git a/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c index 14b6685..84a5f11 100644 --- a/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c +++ b/board/freescale/mx7ulp_arm2/mx7ulp_arm2.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,6 +24,9 @@ DECLARE_GLOBAL_DATA_PTR; #define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE) +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE) + #define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) #define QSPI_PAD_CTRL0 (PAD_CTL_PUS_UP | PAD_CTL_DSE \ @@ -73,12 +77,12 @@ static void setup_iomux_uart(void) static iomux_cfg_t const usb_otg1_pads[] = { #ifdef CONFIG_TARGET_MX7ULP_10X10_ARM2 - MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* gpio for otgid */ - MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* gpio for power en */ + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ + MX7ULP_PAD_PTC1__PTC1 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ #else /*Need rework for ID and PWR_EN pins on 14x14 ARM2*/ - MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* gpio for otgid */ - MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* gpio for power en */ + MX7ULP_PAD_PTC18__PTC18 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for otgid */ + MX7ULP_PAD_PTA31__PTA31 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ #endif }; diff --git a/board/freescale/mx7ulp_evk/mx7ulp_evk.c b/board/freescale/mx7ulp_evk/mx7ulp_evk.c index 2939915..5ba35cf 100644 --- a/board/freescale/mx7ulp_evk/mx7ulp_evk.c +++ b/board/freescale/mx7ulp_evk/mx7ulp_evk.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ */ @@ -23,7 +24,8 @@ DECLARE_GLOBAL_DATA_PTR; #define I2C_PAD_CTRL (PAD_CTL_PUS_UP | PAD_CTL_ODE) -#define GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE | PAD_CTL_IBE_ENABLE) +#define OTG_ID_GPIO_PAD_CTRL (PAD_CTL_IBE_ENABLE) +#define OTG_PWR_GPIO_PAD_CTRL (PAD_CTL_OBE_ENABLE) #define QSPI_PAD_CTRL1 (PAD_CTL_PUS_UP | PAD_CTL_DSE) @@ -80,8 +82,8 @@ void i2c_init_board(void) #ifdef CONFIG_USB_EHCI_MX7 /*Need rework for ID and PWR_EN pins*/ static iomux_cfg_t const usb_otg1_pads[] = { - MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* gpio for power en */ - MX7ULP_PAD_PTC8__PTC8 | MUX_PAD_CTRL(GPIO_PAD_CTRL), /* gpio for OTG ID*/ + MX7ULP_PAD_PTC0__PTC0 | MUX_PAD_CTRL(OTG_PWR_GPIO_PAD_CTRL), /* gpio for power en */ + MX7ULP_PAD_PTC8__PTC8 | MUX_PAD_CTRL(OTG_ID_GPIO_PAD_CTRL), /* gpio for OTG ID*/ }; static void setup_usb(void) |