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| author | Bai Ping <ping.bai@nxp.com> | 2017-02-09 13:50:32 +0800 |
|---|---|---|
| committer | Bai Ping <ping.bai@nxp.com> | 2017-02-09 14:59:57 +0800 |
| commit | 7c9a3573ec0191f1e0bea12956346a5eab2db43a (patch) | |
| tree | a92d7c1572da92f7608eb050c501f46e2c5b2d7f | |
| parent | 2b29c1873c2293abe1c4b361392521223b9c9ecf (diff) | |
| download | u-boot-imx-7c9a3573ec0191f1e0bea12956346a5eab2db43a.zip u-boot-imx-7c9a3573ec0191f1e0bea12956346a5eab2db43a.tar.gz u-boot-imx-7c9a3573ec0191f1e0bea12956346a5eab2db43a.tar.bz2 | |
MLK-13899 ARM: mx7ulp: Correct the clock index on imx7ulp
On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
| -rw-r--r-- | arch/arm/cpu/armv7/mx7ulp/scg.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx7ulp/scg.c b/arch/arm/cpu/armv7/mx7ulp/scg.c index daf1c61..35d962c 100644 --- a/arch/arm/cpu/armv7/mx7ulp/scg.c +++ b/arch/arm/cpu/armv7/mx7ulp/scg.c @@ -1,5 +1,6 @@ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -436,7 +437,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk) case SCG_SCS_SLOW_IRC: case SCG_SCS_FAST_IRC: case SCG_SCS_RTC_OSC: - rate = scg_src_get_rate(scg_scs_array[val]); + rate = scg_src_get_rate(scg_scs_array[val - 1]); break; case 5: rate = scg_apll_get_rate(); |