MLK-13749 mx7ulp_arm2: Enable MX7ULP 10x10 ARM2 board build

Add the lpddr2 support from script "IMX7ULP1_LPDDR2_320MHz_1GB_32bit_V1.0.inc"
and build target file for the 10x10 ARM2 board.

Signed-off-by: Ye Li <ye.li@nxp.com>

3 files changed, 309 insertions, 0 deletions

diff --git a/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg b/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg
new file mode 100644
index 0000000..5031c12
--- /dev/null
+++ b/board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg
@@ -0,0 +1,138 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#define __ASSEMBLY__
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi/sd/nand/onenand, qspi/nor
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx7ulp_arm2/plugin.bin 0x2F020000
+#else
+
+#ifdef CONFIG_SECURE_BOOT
+CSF CONFIG_CSF_SIZE
+#endif
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4   0x403f00e0 0x00000000
+DATA 4   0x403e0040 0x01000020
+DATA 4   0x403e0500 0x01000000
+DATA 4   0x403e050c 0x80808080
+DATA 4   0x403e0508 0x00140000
+DATA 4   0x403E0510 0x00000004
+DATA 4   0x403E0514 0x00000002
+DATA 4   0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4   0x403e050c 0x8080801E
+CHECK_BITS_SET 4 0x403e050c 0x00000040
+DATA 4   0x403E0030 0x00000001
+DATA 4   0x403e0040 0x11000020
+DATA 4   0x403f00e0 0x42000000
+
+DATA 4   0x40B300AC 0x40000000
+
+DATA 4   0x40AD0128 0x00040000
+DATA 4   0x40AD00F8 0x00000000
+DATA 4   0x40AD00D8 0x0000018C
+DATA 4   0x40AD0108 0x00000180
+DATA 4   0x40AD0104 0x00000180
+DATA 4   0x40AD0124 0x00010000
+DATA 4   0x40AD0080 0x0000018C
+DATA 4   0x40AD0084 0x0000018C
+DATA 4   0x40AD0088 0x0000018C
+DATA 4   0x40AD008C 0x0000018C
+
+DATA 4   0x40AD0120 0x00010000
+DATA 4   0x40AD010C 0x00000180
+DATA 4   0x40AD0110 0x00000180
+DATA 4   0x40AD0114 0x00000180
+DATA 4   0x40AD0118 0x00000180
+DATA 4   0x40AD0090 0x00000180
+DATA 4   0x40AD0094 0x00000180
+DATA 4   0x40AD0098 0x00000180
+DATA 4   0x40AD009C 0x00000180
+
+DATA 4   0x40AD00E0 0x00040000
+DATA 4   0x40AD00E4 0x00040000
+
+DATA 4   0x40AB001C 0x00008000
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB085C 0x0D3900A0
+DATA 4   0x40AB0890 0x00400000
+
+DATA 4   0x40AB0848 0x40404040
+DATA 4   0x40AB0850 0x40404040
+DATA 4   0x40AB081C 0x33333333
+DATA 4   0x40AB0820 0x33333333
+DATA 4   0x40AB0824 0x33333333
+DATA 4   0x40AB0828 0x33333333
+
+DATA 4   0x40AB082C 0xf3333333
+DATA 4   0x40AB0830 0xf3333333
+DATA 4   0x40AB0834 0xf3333333
+DATA 4   0x40AB0838 0xf3333333
+
+DATA 4   0x40AB08C0 0x24922492
+DATA 4   0x40AB08B8 0x00000800
+
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB000C 0x292C42F3
+DATA 4   0x40AB0010 0x00100A22
+DATA 4   0x40AB0038 0x00120556
+DATA 4   0x40AB0014 0x00C700DB
+DATA 4   0x40AB0018 0x00211708
+DATA 4   0x40AB002C 0x0F9F26D2
+DATA 4   0x40AB0030 0x009F0E10
+DATA 4   0x40AB0040 0x0000003F
+DATA 4   0x40AB0000 0xC3110000
+
+DATA 4   0x40AB001C 0x00008010
+DATA 4   0x40AB001C 0x00008018
+DATA 4   0x40AB001C 0x003F8030
+DATA 4   0x40AB001C 0x003F8038
+DATA 4   0x40AB001C 0xFF0A8030
+DATA 4   0x40AB001C 0xFF0A8038
+DATA 4   0x40AB001C 0x04028030
+DATA 4   0x40AB001C 0x04028038
+DATA 4   0x40AB001C 0x82018030
+DATA 4   0x40AB001C 0x82018038
+DATA 4   0x40AB001C 0x01038030
+DATA 4   0x40AB001C 0x01038038
+
+DATA 4   0x40AB083C 0x20000000
+
+DATA 4   0x40AB0020 0x00001800
+DATA 4   0x40AB0800 0xA1390003
+DATA 4   0x40AB0004 0x00020052
+DATA 4   0x40AB0404 0x00011006
+DATA 4   0x40AB001C 0x00000000
+
+#endif
diff --git a/board/freescale/mx7ulp_arm2/plugin.S b/board/freescale/mx7ulp_arm2/plugin.S
index 8de06c6..4532b67 100644
--- a/board/freescale/mx7ulp_arm2/plugin.S
+++ b/board/freescale/mx7ulp_arm2/plugin.S
@@ -1,5 +1,6 @@
 /*
  * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
@@ -194,6 +195,162 @@ wait2:
 
 .endm
 
+.macro imx7ulp_arm2_lpddr2_setting
+
+	imx7ulp_ddr_freq_decrease
+
+	/* Enable MMDC PCC clock */
+	ldr r2, =0x40b30000
+	ldr r3, =0x40000000
+	str r3, [r2, #0xac]
+
+	/* Configure DDR pad */
+	ldr r0, =0x40ad0000
+	ldr r1, =0x00040000
+	str r1, [r0, #0x128]
+	ldr r1, =0x0
+	str r1, [r0, #0xf8]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0xd8]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x108]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x104]
+	ldr r1, =0x00010000
+	str r1, [r0, #0x124]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x80]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x84]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x88]
+	ldr r1, =0x0000018C
+	str r1, [r0, #0x8c]
+
+	ldr r1, =0x00010000
+	str r1, [r0, #0x120]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x10c]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x110]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x114]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x118]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x90]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x94]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x98]
+	ldr r1, =0x00000180
+	str r1, [r0, #0x9c]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe0]
+	ldr r1, =0x00040000
+	str r1, [r0, #0xe4]
+
+	ldr r0, =0x40ab0000
+	ldr r1, =0x00008000
+	str r1, [r0, #0x1c]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x0D3900A0
+	str r1, [r0, #0x85c]
+	ldr r1, =0x00400000
+	str r1, [r0, #0x890]
+
+	ldr r1, =0x40404040
+	str r1, [r0, #0x848]
+	ldr r1, =0x40404040
+	str r1, [r0, #0x850]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x81c]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x820]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x824]
+	ldr r1, =0x33333333
+	str r1, [r0, #0x828]
+
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x82c]
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x830]
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x834]
+	ldr r1, =0xf3333333
+	str r1, [r0, #0x838]
+
+	ldr r1, =0x24922492
+	str r1, [r0, #0x8c0]
+	ldr r1, =0x00000800
+	str r1, [r0, #0x8b8]
+
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x292C42F3
+	str r1, [r0, #0xc]
+	ldr r1, =0x00100A22
+	str r1, [r0, #0x10]
+	ldr r1, =0x00120556
+	str r1, [r0, #0x38]
+	ldr r1, =0x00C700DB
+	str r1, [r0, #0x14]
+	ldr r1, =0x00211708
+	str r1, [r0, #0x18]
+
+	ldr r1, =0x0F9F26D2
+	str r1, [r0, #0x2c]
+	ldr r1, =0x009F0E10
+	str r1, [r0, #0x30]
+	ldr r1, =0x0000003F
+	str r1, [r0, #0x40]
+	ldr r1, =0xC3110000
+	str r1, [r0, #0x0]
+
+	ldr r1, =0x00008010
+	str r1, [r0, #0x1c]
+	ldr r1, =0x00008018
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x003F8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8030
+	str r1, [r0, #0x1c]
+	ldr r1, =0xFF0A8038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x04028038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x82018038
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038030
+	str r1, [r0, #0x1c]
+	ldr r1, =0x01038038
+	str r1, [r0, #0x1c]
+
+	ldr r1, =0x20000000
+	str r1, [r0, #0x83c]
+
+	ldr r1, =0x00001800
+	str r1, [r0, #0x20]
+	ldr r1, =0xA1390003
+	str r1, [r0, #0x800]
+	ldr r1, =0x00020052
+	str r1, [r0, #0x4]
+	ldr r1, =0x00011006
+	str r1, [r0, #0x404]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x1c]
+
+.endm
+
+
 .macro imx7ulp_clock_gating
 .endm
 
@@ -201,7 +358,11 @@ wait2:
 .endm
 
 .macro imx7ulp_ddr_setting
+#if defined (CONFIG_TARGET_MX7ULP_10X10_ARM2)
+	imx7ulp_arm2_lpddr2_setting
+#else
 	imx7ulp_arm2_lpddr3_setting
+#endif
 .endm
 
 /* include the common plugin code here */
diff --git a/configs/mx7ulp_10x10_arm2_defconfig b/configs/mx7ulp_10x10_arm2_defconfig
new file mode 100644
index 0000000..e0875b2
--- /dev/null
+++ b/configs/mx7ulp_10x10_arm2_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7ulp_arm2/imximage_lpddr2.cfg"
+CONFIG_ARM=y
+CONFIG_ARCH_MX7ULP=y
+CONFIG_TARGET_MX7ULP_10X10_ARM2=y
+CONFIG_SYS_MALLOC_F=y
+CONFIG_SYS_MALLOC_F_LEN=0x400
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
+CONFIG_DM_GPIO=y
+CONFIG_IMX_RGPIO2P=y