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authorMichal Simek <michal.simek@xilinx.com>2015-11-30 10:09:43 +0100
committerMichal Simek <michal.simek@xilinx.com>2015-12-07 09:59:04 +0100
commit3fac27243c1ee4bdf903bac031e522f97e27ef44 (patch)
tree876c141ea08df37b2cb289541cec3feb07cce670
parentb904725a112f7b7a1b5d657541d77dc8fa1a1615 (diff)
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net: gem: Change mdio_wait prototype to pass regs
Pass regs instead of dev because this will be chagned by driver model. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
-rw-r--r--drivers/net/zynq_gem.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 1a5a366..7f801d5 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -172,9 +172,8 @@ struct zynq_gem_priv {
struct mii_dev *bus;
};
-static inline int mdio_wait(struct eth_device *dev)
+static inline int mdio_wait(struct zynq_gem_regs *regs)
{
- struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
u32 timeout = 20000;
/* Wait till MDIO interface is ready to accept a new transaction. */
@@ -198,7 +197,7 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
u32 mgtcr;
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
- if (mdio_wait(dev))
+ if (mdio_wait(regs))
return 1;
/* Construct mgtcr mask for the operation */
@@ -209,7 +208,7 @@ static u32 phy_setup_op(struct eth_device *dev, u32 phy_addr, u32 regnum,
/* Write mgtcr and wait for completion */
writel(mgtcr, &regs->phymntnc);
- if (mdio_wait(dev))
+ if (mdio_wait(regs))
return 1;
if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK)