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| author | Stefan Roese <sr@denx.de> | 2007-12-26 20:20:19 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-12-27 19:35:35 +0100 |
| commit | 2e583d6c81034f80a267b89fa55498ae063ccef1 (patch) | |
| tree | 101876e599503733f565c720eadc36764399938f | |
| parent | 42d55ea0bde06e47d5a3b49b0d91002acd8e5708 (diff) | |
| download | u-boot-imx-2e583d6c81034f80a267b89fa55498ae063ccef1.zip u-boot-imx-2e583d6c81034f80a267b89fa55498ae063ccef1.tar.gz u-boot-imx-2e583d6c81034f80a267b89fa55498ae063ccef1.tar.bz2 | |
ppc4xx: Fix compilation problem in 405 cache POST test
Signed-off-by: Stefan Roese <sr@denx.de>
| -rw-r--r-- | post/cpu/ppc4xx/cache.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c index c8ddf35..c86a150 100644 --- a/post/cpu/ppc4xx/cache.c +++ b/post/cpu/ppc4xx/cache.c @@ -61,6 +61,7 @@ int cache_post_test (int flags) void *virt = (void *)CFG_POST_CACHE_ADDR; int ints; int res = 0; + int tlb = -1; /* index to the victim TLB entry */ /* * All 44x variants deal with cache management differently @@ -70,7 +71,6 @@ int cache_post_test (int flags) */ #ifdef CONFIG_440 int word0, i; - int tlb; /* index to the victim TLB entry */ /* * Allocate a new TLB entry, since we are going to modify |