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| author | Haibo Chen <haibo.chen@nxp.com> | 2016-11-04 14:29:51 +0800 |
|---|---|---|
| committer | Haibo Chen <haibo.chen@nxp.com> | 2016-11-04 14:29:51 +0800 |
| commit | 07abbd4e5c5006ab7adc6a4f3655e9a0817c7cb1 (patch) | |
| tree | 6333af8a4de9843ea6b03328bd29bfd9216af595 | |
| parent | 0df1d6537bef13c1846c6762e78938a304e083b0 (diff) | |
| download | u-boot-imx-07abbd4e5c5006ab7adc6a4f3655e9a0817c7cb1.zip u-boot-imx-07abbd4e5c5006ab7adc6a4f3655e9a0817c7cb1.tar.gz u-boot-imx-07abbd4e5c5006ab7adc6a4f3655e9a0817c7cb1.tar.bz2 | |
MLK-13405-4 mx6sll-arm2: change the eMMC reset pad to 1.8v
eMMC is connected fixed to 1.8v, so need to set the LVE of pad
sd2_rst. Also need to set the VSELECT to change all the eMMC pad
(cmd, clk, data) I/O voltage to 1.8v. Otherwise, the current leak
will pull up the VCCQ from 1.8v to 2.6v, which will impact SD1 and
SD3 voltage switch.
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| -rw-r--r-- | board/freescale/mx6sll_arm2/mx6sll_arm2.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/board/freescale/mx6sll_arm2/mx6sll_arm2.c b/board/freescale/mx6sll_arm2/mx6sll_arm2.c index e7b8f5a..9094586 100644 --- a/board/freescale/mx6sll_arm2/mx6sll_arm2.c +++ b/board/freescale/mx6sll_arm2/mx6sll_arm2.c @@ -153,7 +153,7 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { /* DQS */ MX6_PAD_GPIO4_IO21__SD2_STROBE | MUX_PAD_CTRL(NO_PAD_CTRL), /* RST_B */ - MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_RESET__GPIO4_IO27 | MUX_PAD_CTRL(USDHC_PAD_CTRL | PAD_CTL_LVE), }; /* Wifi SD */ @@ -220,7 +220,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { - int i; + int i, ret; /* * According to the board_mmc_init() the following map is done: @@ -241,6 +241,10 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads( usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + /* eMMC connect to 1.8v, so need to set eMMC I/O voltage to 1.8v */ + ret = readl(usdhc_cfg[1].esdhc_base + 0xc0); /* vend_spec */ + ret |= 0x2; + writel(ret, (usdhc_cfg[1].esdhc_base + 0xc0)); gpio_direction_output(USDHC2_PWR_GPIO, 1); break; case 2: |