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| author | Ye Li <ye.li@nxp.com> | 2016-11-24 10:49:57 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-11-25 14:51:51 +0800 |
| commit | f51ca6e0c4f273eba7413ece74fa405dff06771c (patch) | |
| tree | bd70ec48d6b2d5175497b5f9a14eb37cd5588deb | |
| parent | 8e0351e7d524a1d53b596710972e074487d9d1fe (diff) | |
| download | u-boot-imx-f51ca6e0c4f273eba7413ece74fa405dff06771c.zip u-boot-imx-f51ca6e0c4f273eba7413ece74fa405dff06771c.tar.gz u-boot-imx-f51ca6e0c4f273eba7413ece74fa405dff06771c.tar.bz2 | |
MLK-13509 mx7ulp_evk: Update DDR script to v1.2
DDR script is updated to v1.2 for EVK board to fix DQS gating issue
and add pre-charge .That DQS sampling may have problem after we enabling
the SDE_0/SDE_1 in MDCTL.
Changes:
-Issue a Precharge-All command prior to the MRW Reset command.
setmem /32 0x40AB001C = 0x00008050 // [MMDC_MDSCR] precharge all to CS0
-Based on V1.1, move the "Read DQS Gating Disable" to the step after "MR setting",
to avoid potential DDR initializaiton failures (especially in Plugin Mode).
File:
EVK_IMX7ULP1_LPDDR3_320MHz_1GB_32bit_V1.2.inc
Test:
Passed stress test on 1 board.
Signed-off-by: Ye Li <ye.li@nxp.com>
| -rw-r--r-- | board/freescale/mx7ulp_evk/imximage.cfg | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg index ce85e50..2064630 100644 --- a/board/freescale/mx7ulp_evk/imximage.cfg +++ b/board/freescale/mx7ulp_evk/imximage.cfg @@ -114,8 +114,9 @@ DATA 4 0x40AB002C 0x0F9F26D2 DATA 4 0x40AB0030 0x009F0E10 DATA 4 0x40AB0040 0x0000003F DATA 4 0x40AB0000 0xC3190000 -DATA 4 0x40AB083C 0x20000000 +DATA 4 0x40AB001C 0x00008050 +DATA 4 0x40AB001C 0x00008058 DATA 4 0x40AB001C 0x003F8030 DATA 4 0x40AB001C 0x003F8038 DATA 4 0x40AB001C 0xFF0A8030 @@ -127,6 +128,8 @@ DATA 4 0x40AB001C 0x83018038 DATA 4 0x40AB001C 0x01038030 DATA 4 0x40AB001C 0x01038038 +DATA 4 0x40AB083C 0x20000000 + DATA 4 0x40AB0020 0x00001800 DATA 4 0x40AB0800 0xA1310000 DATA 4 0x40AB0004 0x00020052 |