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| author | Ye Li <ye.li@nxp.com> | 2016-11-17 10:37:06 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-11-22 17:49:33 +0800 |
| commit | b8f4a3546fcad61f03aa685366772f2408dbb5f4 (patch) | |
| tree | c2ad4fd060c77d8389d2ccb6a450b105bb9c11c3 | |
| parent | 8dfdf83abaff44efb487f801cd1757a729d427c5 (diff) | |
| download | u-boot-imx-b8f4a3546fcad61f03aa685366772f2408dbb5f4.zip u-boot-imx-b8f4a3546fcad61f03aa685366772f2408dbb5f4.tar.gz u-boot-imx-b8f4a3546fcad61f03aa685366772f2408dbb5f4.tar.bz2 | |
MLK-13450-16 fsl_qspi: Update changes for mx7ulp
The mx7ulp has small TX/RX FIFO (64Bytes) and AHB buffer size (128Bytes)
than other i.MX. Change some parameters for it.
Also found when the DDR_EN bit is set, sometime the page programming will fail
during large data programming. The 64 bytes data is not programmed into flash.
But when DDR_EN is clear, there is no such issue. Suspect this is a IC issue.
We have disable the DDR_EN for mx7ulp.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | drivers/spi/fsl_qspi.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 1e15bb5..2b27e86 100644 --- a/drivers/spi/fsl_qspi.c +++ b/drivers/spi/fsl_qspi.c @@ -418,6 +418,7 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) fsl_qspi_lock_lut(q); } +#ifndef CONFIG_MX7ULP /*Enable DDR Read Mode*/ static void fsl_enable_ddr_mode(struct fsl_qspi *q) { @@ -441,6 +442,7 @@ static void fsl_enable_ddr_mode(struct fsl_qspi *q) writel(reg, base + QUADSPI_MCR); } +#endif /* * There are two different ways to read out the data from the flash: @@ -473,8 +475,14 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR); writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR); writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR); + +#ifdef CONFIG_MX7ULP + writel(QUADSPI_BUF3CR_ALLMST_MASK | (0x10 << QUADSPI_BUF3CR_ADATSZ_SHIFT), + base + QUADSPI_BUF3CR); +#else writel(QUADSPI_BUF3CR_ALLMST_MASK | (0x80 << QUADSPI_BUF3CR_ADATSZ_SHIFT), base + QUADSPI_BUF3CR); +#endif /* We only use the buffer3 */ writel(0, base + QUADSPI_BUF0IND); @@ -485,8 +493,10 @@ static void fsl_qspi_init_abh_read(struct fsl_qspi *q) writel(SEQID_FAST_READ << QUADSPI_BFGENCR_SEQID_SHIFT, base + QUADSPI_BFGENCR); +#ifndef CONFIG_MX7ULP /*Enable DDR Mode*/ fsl_enable_ddr_mode(q); +#endif } static int fsl_qspi_init(struct fsl_qspi *q) @@ -501,8 +511,13 @@ static int fsl_qspi_init(struct fsl_qspi *q) return 1; } q->devtype_data = ptr; +#ifdef CONFIG_MX7ULP + q->devtype_data->rxfifo = 64; + q->devtype_data->txfifo = 64; +#else q->devtype_data->rxfifo = 128; q->devtype_data->txfifo = 512; +#endif /* init the LUT table */ fsl_qspi_init_lut(q); @@ -818,7 +833,7 @@ static void fsl_qspi_write_data(struct fsl_qspi *q, int len, u8* txbuf) writel(tmp, q->iobase + QUADSPI_TBDR); } -#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL) +#if defined(CONFIG_MX7D) || defined(CONFIG_MX6UL) || defined(CONFIG_MX7ULP) u32 t3; /* iMX7D and MX6UL TXFIFO must be at least 16 bytes*/ t3 = t1 + ((t2 + 3) >> 2); |