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authorAdrian Alonso <adrian.alonso@nxp.com>2016-11-29 11:38:18 -0600
committerAdrian Alonso <adrian.alonso@nxp.com>2016-12-01 11:29:17 -0600
commit73ff17548cb04733a50dd6c753b3931a8b772e9d (patch)
treeba72c4aa5d012f7911e32d9d932940d61dced146
parent498f4a791593069220213c6d777527f4d899fb8a (diff)
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MLK-13540-1: mx6sx: arm2: lpddr2: add pre charge command all
LPDDR2 script MX6SX_19x19_LPDDR2_JEDEC.inc Updated to add Precharge all command per JEDEC The memory controller may optionally issue a precharge-all command prior to the MRW reset command This is strongly recommended to ensure robust DRAM initialization Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com>
-rw-r--r--board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg2
-rw-r--r--board/freescale/mx6sx_17x17_arm2/plugin.S4
2 files changed, 6 insertions, 0 deletions
diff --git a/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg b/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg
index afb780e..011e385 100644
--- a/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg
+++ b/board/freescale/mx6sx_17x17_arm2/mx6sx_14x14_lpddr2_arm2.cfg
@@ -130,12 +130,14 @@ DATA 4 0x021b0008 0x00000000
DATA 4 0x021b0040 0x0000004f
DATA 4 0x021b0000 0xc3110000
+DATA 4 0x021b001c 0x00008050
DATA 4 0x021b001c 0x003f8030
DATA 4 0x021b001c 0xff0a8030
DATA 4 0x021b001c 0x82018030
DATA 4 0x021b001c 0x04028030
DATA 4 0x021b001c 0x01038030
+DATA 4 0x021b001c 0x00008058
DATA 4 0x021b001c 0x003f8038
DATA 4 0x021b001c 0xff0a8038
DATA 4 0x021b001c 0x82018038
diff --git a/board/freescale/mx6sx_17x17_arm2/plugin.S b/board/freescale/mx6sx_17x17_arm2/plugin.S
index bce001e..d4f12e7 100644
--- a/board/freescale/mx6sx_17x17_arm2/plugin.S
+++ b/board/freescale/mx6sx_17x17_arm2/plugin.S
@@ -229,6 +229,8 @@
ldr r2, =0xc3110000
str r2, [r0, #0x000]
+ ldr r2, =0x00008050
+ str r2, [r0, #0x01c]
ldr r2, =0x003f8030
str r2, [r0, #0x01c]
ldr r2, =0xff0a8030
@@ -240,6 +242,8 @@
ldr r2, =0x01038030
str r2, [r0, #0x01c]
+ ldr r2, =0x00008058
+ str r2, [r0, #0x01c]
ldr r2, =0x003f8038
str r2, [r0, #0x01c]
ldr r2, =0xff0a8038