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| author | Peng Fan <Peng.Fan@freescale.com> | 2015-04-17 18:28:29 +0800 |
|---|---|---|
| committer | Ye Li <ye.li@nxp.com> | 2016-03-25 16:21:00 +0800 |
| commit | 3d25e2acd48f605678a98cf594a715809dea8286 (patch) | |
| tree | fa36974ae04546cc97ec76dc6c9418b19319b048 | |
| parent | 7df52f9518298899dfe361cb5a713d371ea6aa9b (diff) | |
| download | u-boot-imx-3d25e2acd48f605678a98cf594a715809dea8286.zip u-boot-imx-3d25e2acd48f605678a98cf594a715809dea8286.tar.gz u-boot-imx-3d25e2acd48f605678a98cf594a715809dea8286.tar.bz2 | |
MLK-10674-2 imx: mx6qp settings for PRE
Since the following piece settings can not be in DCD table, we
add them in enable_ipu_clock.
"
setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator
setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator
setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0
setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1
setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2
setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3
setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0
setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1
setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2
setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE
"
CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h,
the settings sure will effect.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 89f097b..afcbcad 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -1302,7 +1302,30 @@ int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } -#ifndef CONFIG_MX6SX +static void pre_misc_setting(void) +{ + /* Bypass IPU1 QoS generator */ + writel(0x00000002, 0x00bb048c); + /* Bypass IPU2 QoS generator */ + writel(0x00000002, 0x00bb050c); + /* Bandwidth THR for of PRE0 */ + writel(0x00000200, 0x00bb0690); + /* Bandwidth THR for of PRE1 */ + writel(0x00000200, 0x00bb0710); + /* Bandwidth THR for of PRE2 */ + writel(0x00000200, 0x00bb0790); + /* Bandwidth THR for of PRE3 */ + writel(0x00000200, 0x00bb0810); + /* Saturation THR for of PRE0 */ + writel(0x00000020, 0x00bb0694); + /* Saturation THR for of PRE1 */ + writel(0x00000020, 0x00bb0714); + /* Saturation THR for of PRE2 */ + writel(0x00000020, 0x00bb0794); + /* Saturation THR for of PRE */ + writel(0x00000020, 0x00bb0814); +} + void enable_ipu_clock(void) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -1314,9 +1337,16 @@ void enable_ipu_clock(void) if (is_mx6dqp()) { setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK); setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK); + + /* + * Since CONFIG_VIDEO_IPUV3 is always set in mx6sabre_common.h and + * this misc setting is a must for mx6qp, this position is ok + * to do such settings. + */ + pre_misc_setting(); } } -#endif + /***************************************************/ U_BOOT_CMD( |