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| author | Liviu Dudau <Liviu.Dudau@foss.arm.com> | 2015-10-19 11:08:31 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2015-10-19 17:05:28 -0400 |
| commit | 2d0cee1ca2b9d977fa3214896bb2e30cfec77059 (patch) | |
| tree | cf901bf536c12645ac509dcf9782f2156082f160 | |
| parent | 2727f3bfba1bc78ca517984c2c9e0c473aeedbf4 (diff) | |
| download | u-boot-imx-2d0cee1ca2b9d977fa3214896bb2e30cfec77059.zip u-boot-imx-2d0cee1ca2b9d977fa3214896bb2e30cfec77059.tar.gz u-boot-imx-2d0cee1ca2b9d977fa3214896bb2e30cfec77059.tar.bz2 | |
vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
| -rw-r--r-- | board/armltd/vexpress64/vexpress64.c | 8 | ||||
| -rw-r--r-- | include/configs/vexpress_aemv8a.h | 4 |
2 files changed, 11 insertions, 1 deletions
diff --git a/board/armltd/vexpress64/vexpress64.c b/board/armltd/vexpress64/vexpress64.c index 7cb4e00..6df9d60 100644 --- a/board/armltd/vexpress64/vexpress64.c +++ b/board/armltd/vexpress64/vexpress64.c @@ -38,6 +38,14 @@ int dram_init(void) return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; +} + /* * Board specific reset that is system reset. */ diff --git a/include/configs/vexpress_aemv8a.h b/include/configs/vexpress_aemv8a.h index ef3014d..0f2f1a3 100644 --- a/include/configs/vexpress_aemv8a.h +++ b/include/configs/vexpress_aemv8a.h @@ -168,11 +168,13 @@ #define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x10000000) /* Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_NR_DRAM_BANKS 2 #define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */ +#define PHYS_SDRAM_2 (0x880000000) /* Top 16MB reserved for secure world use */ #define DRAM_SEC_SIZE 0x01000000 #define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE +#define PHYS_SDRAM_2_SIZE 0x180000000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 /* Enable memtest */ |