MLK-13450-7 mx7ulp: Add M4 core boot support when using single boot mode

The single boot mode in MX7ULP will only boot up A7, the M4 is running in ROM
by checking entry from SIM0 GP register.

In this patch, We bind M4 image with u-boot.bin before attaching the imx header.
So the whole image (included M4 image) will be loaded by A7 ROM into DDR. Then
when u-boot is up, it will try to load M4 image into TCML and boot it there.

Since M4 image will not be relocated in u-boot codes, we must load it during
board_f. Current implementation put it in arch_cpu_init to get M4 booted
as quick as possible.

We requires the M4 image with IVT head and padding embedded, not a RAW binary. The
image should be same as what is used for M4 QSPI boot in dual boot mode.

Signed-off-by: Ye Li <ye.li@nxp.com>

2 files changed, 46 insertions, 0 deletions

diff --git a/Makefile b/Makefile
index ad9d566..6eb4538 100644
--- a/Makefile
+++ b/Makefile
@@ -829,9 +829,15 @@ u-boot-dtb.bin: u-boot-nodtb.bin dts/dt.dtb FORCE
 u-boot.bin: u-boot-dtb.bin FORCE
 	$(call if_changed,copy)
 else
+
+ifeq ($(CONFIG_IMX_M4_BIND),y)
+u-boot.bin: u-boot-nodtb.bin ulp_m4.bin FORCE
+	$(call if_changed,cat)
+else
 u-boot.bin: u-boot-nodtb.bin FORCE
 	$(call if_changed,copy)
 endif
+endif
 
 %.imx: %.bin
 	$(Q)$(MAKE) $(build)=arch/arm/imx-common $@
diff --git a/arch/arm/cpu/armv7/mx7ulp/soc.c b/arch/arm/cpu/armv7/mx7ulp/soc.c
index 5caa8dd..bffd212 100644
--- a/arch/arm/cpu/armv7/mx7ulp/soc.c
+++ b/arch/arm/cpu/armv7/mx7ulp/soc.c
@@ -6,6 +6,7 @@
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
+#include <asm/sections.h>
 #include <asm/arch/sys_proto.h>
 
 static char *get_reset_cause(char *);
@@ -41,8 +42,43 @@ enum bt_mode get_boot_mode(void)
 	return LOW_POWER_BOOT;
 }
 
+#ifdef CONFIG_IMX_M4_BIND
+int mcore_early_load_and_boot(void)
+{
+	u32 *src_addr = (u32 *)&_end;
+	u32 *dest_addr = (u32 *)TCML_BASE; /*TCML*/
+	u32 image_size = SIZE_128K + SIZE_64K; /* 192 KB*/
+	u32 pc = 0, tag = 0;
+
+	memcpy(dest_addr, src_addr, image_size);
+
+	/* Set GP register to tell the M4 rom the image entry */
+	/* We assume the M4 image has IVT head and padding which
+	 * should be same as the one programmed into QSPI flash
+	 */
+	tag = *(dest_addr + 1024);
+	if (tag != 0x402000d1)
+		return -1;
+
+	pc = *(dest_addr + 1025);
+
+	writel(pc, SIM0_RBASE + 0x70); /*GP7*/
+
+	return 0;
+}
+#endif
+
 int arch_cpu_init(void)
 {
+#ifdef CONFIG_IMX_M4_BIND
+	int ret;
+	if (get_boot_mode() == SINGLE_BOOT) {
+		ret = mcore_early_load_and_boot();
+		if (ret)
+			puts("Invalid M4 image, boot failed\n");
+	}
+#endif
+
 	return 0;
 }
 
@@ -203,6 +239,10 @@ int print_cpuinfo(void)
 	case SINGLE_BOOT:
 	default:
 		printf("Single boot\n");
+#ifdef CONFIG_IMX_M4_BIND
+		if (readl(SIM0_RBASE + 0x70))
+			printf("M4 start at 0x%x\n", readl(SIM0_RBASE + 0x70));
+#endif
 		break;
 	}