diff options
| author | Fabio Estevam <fabio.estevam@nxp.com> | 2016-07-18 10:19:28 -0300 |
|---|---|---|
| committer | Robby Cai <robby.cai@nxp.com> | 2016-11-16 16:50:45 +0800 |
| commit | b1d44083fa42d996927ced35762ca6d9f0626615 (patch) | |
| tree | 8a1eef45e4a336148b13c31c3aa7ce9b6b0d8b46 | |
| parent | ec33bbb3e2cee90826082142fe5a6661a3faf908 (diff) | |
| download | u-boot-imx-b1d44083fa42d996927ced35762ca6d9f0626615.zip u-boot-imx-b1d44083fa42d996927ced35762ca6d9f0626615.tar.gz u-boot-imx-b1d44083fa42d996927ced35762ca6d9f0626615.tar.bz2 | |
mx6: clock: Fix the logic for reading axi_alt_sel
According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
(cherry picked from commit 8f2e2f15ffa1bb03b6e6e189312426059f3215d1)
(cherry picked from commit 697f9ffc0eea9facf2fdaf596f008560db42ea7d)
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 0cb576f..f93475a 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -456,9 +456,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = mxc_get_pll_pfd(PLL_BUS, 2); - else root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); + else + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); } else root_freq = get_periph_clk(); |