diff options
| author | Ye Li <ye.li@nxp.com> | 2017-04-20 10:16:24 +0800 |
|---|---|---|
| committer | Robby Cai <robby.cai@gmail.com> | 2017-05-02 10:45:11 +0800 |
| commit | a57b13b942d59719e3621179e98bd8a0ab235088 (patch) | |
| tree | 8eb8949c667b296ac6264bdf2f5643600ce8ad88 | |
| parent | 568c9c9914863f20a2404c49db0b5ed7541a76ce (diff) | |
| download | u-boot-imx-a57b13b942d59719e3621179e98bd8a0ab235088.zip u-boot-imx-a57b13b942d59719e3621179e98bd8a0ab235088.tar.gz u-boot-imx-a57b13b942d59719e3621179e98bd8a0ab235088.tar.bz2 | |
MLK-14707 fsl_esdhc: Fix eMMC 1.8v setting issuerel_imx_4.1.15_2.1.0_gaimx_v2016.03_4.1.15_2.0.0_ga
Current USDHC driver will reset VSELECT to 0 (3.3v) during mmc init,
then set to 1 for 1.8v eMMC I/O. When booting from eMMC, since ROM has
already set VSELECT to 1.8v before running the u-boot. This reset in
USDHC driver causes a short 2.2v pulse on CMD pin.
Fix this issue by not reset VSELECT to 0 when 1.8v flag is set.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f01ebfdaa57b4c74ede32a6a40cf9cf9184ce049)
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index d357946..fcfb654 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -611,7 +611,10 @@ static int esdhc_init(struct mmc *mmc) esdhc_write32(®s->clktunectrlstatus, 0x0); /* Put VEND_SPEC to default value */ - esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); + if (cfg->vs18_enable) + esdhc_write32(®s->vendorspec, (VENDORSPEC_INIT | ESDHC_VENDORSPEC_VSELECT)); + else + esdhc_write32(®s->vendorspec, VENDORSPEC_INIT); /* Disable DLL_CTRL delay line */ esdhc_write32(®s->dllctrl, 0x0); @@ -640,9 +643,6 @@ static int esdhc_init(struct mmc *mmc) /* Set timout to the maximum value */ esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); - if (cfg->vs18_enable) - esdhc_setbits32(®s->vendorspec, ESDHC_VENDORSPEC_VSELECT); - return 0; } |