MLK-13307-12 imx: mx6: update ccm macro settings for i.MX6SLL

Update CCM macros for i.MX6SLL.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye.Li <ye.li@nxp.com>
(cherry picked from commit f735f8ac328aa49759f6db524f7c2ba32622f711)

1 files changed, 71 insertions, 6 deletions

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index c85e918..ba0aefb 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -265,11 +265,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET		29
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK		(0x7 << 26)
 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET		26
-/* LCDIF on i.MX6SX/UL */
+/* LCDIF on i.MX6SX/UL/SLL */
 #define MXC_CCM_CBCMR_LCDIF1_PODF_MASK                  (0x7 << 23)
 #define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET                23
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 23)
-#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		23
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_PODF_OFFSET		23
+
+/* For i.MX6SL */
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK		(0x7 << 29)
+#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET		29
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_MASK		(0x7 << 26)
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_PODF_OFFSET		26
+#define MXC_CCM_CBCMR_EPDC_PIX_PODF_MASK		(0x7 << 23)
+#define MXC_CCM_CBCMR_EPDC_PIX_PODF_OFFSET		23
+
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK		(0x3 << 21)
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET	21
 #define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL			(1 << 20)
@@ -291,6 +300,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET	8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK		(0x3 << 4)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET		4
+
+/* For i.MX6SL */
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_MASK		(0x3 << 8)
+#define MXC_CCM_CBCMR_GPU2D_CORE_CLK_SEL_OFFSET	8
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_MASK		(0x3 << 4)
+#define MXC_CCM_CBCMR_GPU2D_OVG_CORE_CLK_SEL_OFFSET		4
+
+
 /* Exists on i.MX6QP */
 #define MXC_CCM_CBCMR_PRE_CLK_SEL			(1 << 1)
 
@@ -307,6 +324,9 @@ struct mxc_ccm_reg {
 /* LCFIF2_PODF on i.MX6SX */
 #define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK			(0x7 << 20)
 #define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET               20
+/* LCDIF_PIX_PODF on i.MX6SL */
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_MASK			(0x7 << 20)
+#define MXC_CCM_CSCMR1_LCDIF_PIX_PODF_OFFSET               20
 /* ACLK_EMI on i.MX6DQ/SDL/DQP */
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK		(0x7 << 20)
 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET		20
@@ -497,7 +517,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK		(0x7)
 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET		0
 
-/* i.MX6ULL */
+/* i.MX6ULL/SLL */
 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_MASK		(0x7 << 15)
 #define MXC_CCM_CHSCCDR_EPDC_PRE_CLK_SEL_OFFSET		15
 #define MXC_CCM_CHSCCDR_EPDC_PODF_MASK			(0x7 << 12)
@@ -514,13 +534,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET		19
 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */
 #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK		(0x1 << 18)
-/* LCDIF1 on i.MX6SX/UL */
+/* LCDIF1 on i.MX6SX/UL/SLL */
 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK             (0x7 << 15)
 #define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET           15
 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK              (0x7 << 12)
 #define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET            12
 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK              (0x7 << 9)
 #define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET            9
+
+/* EPDC on i.MX6SL */
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_MASK             (0x7 << 15)
+#define MXC_CCM_CSCDR2_EPDC_PIX_CLK_SEL_OFFSET           15
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_MASK              (0x7 << 12)
+#define MXC_CCM_CSCDR2_EPDC_PIX_PRE_DIV_OFFSET            12
+
 /* LCDIF2 on i.MX6SX */
 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK             (0x7 << 6)
 #define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET           6
@@ -529,6 +556,13 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK              (0x7 << 0)
 #define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET             0
 
+/*LCD on i.MX6SL */
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_MASK             (0x7 << 6)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_CLK_SEL_OFFSET           6
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_MASK              (0x7 << 3)
+#define MXC_CCM_CSCDR2_LCDIF_PIX_PRE_DIV_OFFSET            3
+
+
 /* All IPU2_DI1 are LCDIF1 on MX6SX */
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK	(0x7 << 15)
 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET	15
@@ -554,6 +588,23 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK		(0x3 << 9)
 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET		9
 
+/* For i.MX6SL */
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_LCDIF_AXI_CLK_SEL_OFFSET		14
+#define MXC_CCM_CSCDR3_CSI_CORE_PODF_MASK		(0x7 << 11)
+#define MXC_CCM_CSCDR3_CSI_CORE_PODF_OFFSET		11
+#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_MASK		(0x3 << 9)
+#define MXC_CCM_CSCDR3_CSI_CORE_CLK_SEL_OFFSET		9
+
+/* For i.MX6SLL */
+#define MXC_CCM_CSCDR3_PXP_PODF_MASK		(0x7 << 16)
+#define MXC_CCM_CSCDR3_PXP_PODF_OFFSET		16
+#define MXC_CCM_CSCDR3_PXP_CLK_SEL_MASK		(0x3 << 14)
+#define MXC_CCM_CSCDR3_PXP_CLK_SEL_OFFSET		14
+
+
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY			(1 << 16)
 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY		(1 << 5)
@@ -756,7 +807,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPMUX3_MASK			(3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET	22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK	(3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
-/* i.MX6SX/UL LCD and PXP */
+/* i.MX6SX/UL/SLL LCD and PXP */
 #define MXC_CCM_CCGR2_LCD_OFFSET			28
 #define MXC_CCM_CCGR2_LCD_MASK				(3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET			30
@@ -784,6 +835,20 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_QSPI_OFFSET				14
 #define MXC_CCM_CCGR3_QSPI_MASK					(3 << MXC_CCM_CCGR3_QSPI_OFFSET)
 
+/* i.MX6SL */
+#define MXC_CCM_CCGR3_CSI_CORE_OFFSET			0
+#define MXC_CCM_CCGR3_CSI_CORE_MASK				(3 << MXC_CCM_CCGR3_CSI_CORE_OFFSET)
+#define MXC_CCM_CCGR3_PXP_AXI_OFFSET			2
+#define MXC_CCM_CCGR3_PXP_AXI_MASK				(3 << MXC_CCM_CCGR3_PXP_AXI_OFFSET)
+#define MXC_CCM_CCGR3_EPDC_AXI_OFFSET			4
+#define MXC_CCM_CCGR3_EPDC_AXI_MASK				(3 << MXC_CCM_CCGR3_EPDC_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_AXI_OFFSET			6
+#define MXC_CCM_CCGR3_LCDIF_AXI_MASK			(3 << MXC_CCM_CCGR3_LCDIF_AXI_OFFSET)
+#define MXC_CCM_CCGR3_LCDIF_PIX_OFFSET			8
+#define MXC_CCM_CCGR3_LCDIF_PIX_MASK			(3 << MXC_CCM_CCGR3_LCDIF_PIX_OFFSET)
+#define MXC_CCM_CCGR3_EPDC_PIX_OFFSET			10
+#define MXC_CCM_CCGR3_EPDC_PIX_MASK				(3 << MXC_CCM_CCGR3_EPDC_PIX_OFFSET)
+
 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET				0
 #define MXC_CCM_CCGR3_IPU1_IPU_MASK				(3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET			2