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| author | Hans de Goede <hdegoede@redhat.com> | 2014-12-13 10:25:14 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2015-01-14 14:56:36 +0100 |
| commit | ce881076fc51f281ab28b2a1fde370f10b0c41eb (patch) | |
| tree | 0617165b8f3a91fc2d470d3cd2133a10e6ef148b | |
| parent | b0c4ae1a5176632e17627f05ae54be1b1bea3082 (diff) | |
| download | u-boot-imx-ce881076fc51f281ab28b2a1fde370f10b0c41eb.zip u-boot-imx-ce881076fc51f281ab28b2a1fde370f10b0c41eb.tar.gz u-boot-imx-ce881076fc51f281ab28b2a1fde370f10b0c41eb.tar.bz2 | |
sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
| -rw-r--r-- | arch/arm/cpu/armv7/sunxi/p2wi.c | 14 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/cpu.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 4 |
3 files changed, 10 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/sunxi/p2wi.c b/arch/arm/cpu/armv7/sunxi/p2wi.c index 48613bd..26a9cfc 100644 --- a/arch/arm/cpu/armv7/sunxi/p2wi.c +++ b/arch/arm/cpu/armv7/sunxi/p2wi.c @@ -26,13 +26,13 @@ void p2wi_init(void) { - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; /* Enable p2wi and PIO clk, and de-assert their resets */ prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUNXI_GPL0_R_P2WI_SCK); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUNXI_GPL1_R_P2WI_SDA); + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ writel(P2WI_CTRL_RESET, &p2wi->ctrl); @@ -43,7 +43,7 @@ void p2wi_init(void) int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) { - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; unsigned long tmo = timer_get_us() + 1000000; writel(P2WI_PM_DEV_ADDR(slave_addr) | @@ -62,7 +62,7 @@ int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data) static int p2wi_await_trans(void) { - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; unsigned long tmo = timer_get_us() + 1000000; int ret; u8 reg; @@ -88,7 +88,7 @@ static int p2wi_await_trans(void) int p2wi_read(const u8 addr, u8 *data) { - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; int ret; writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); @@ -105,7 +105,7 @@ int p2wi_read(const u8 addr, u8 *data) int p2wi_write(const u8 addr, u8 data) { - struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUNXI_P2WI_BASE; + struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0); writel(P2WI_DATA_BYTE_1(data), &p2wi->data0); diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h index 9500262..adf203a 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu.h +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -128,7 +128,7 @@ #define SUN6I_CPUCFG_BASE 0x01f01c00 #define SUNXI_R_UART_BASE 0x01f02800 #define SUNXI_R_PIO_BASE 0x01f02c00 -#define SUNXI_P2WI_BASE 0x01f03400 +#define SUN6I_P2WI_BASE 0x01f03400 /* CoreSight Debug Module */ #define SUNXI_CSDM_BASE 0x3f500000 diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 366c0dc..9f972ce 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -173,8 +173,8 @@ enum sunxi_gpio_number { #define SUN4I_GPI4_SDC3 2 -#define SUNXI_GPL0_R_P2WI_SCK 3 -#define SUNXI_GPL1_R_P2WI_SDA 3 +#define SUN6I_GPL0_R_P2WI_SCK 3 +#define SUN6I_GPL1_R_P2WI_SDA 3 #define SUN8I_GPL2_R_UART_TX 2 #define SUN8I_GPL3_R_UART_RX 2 |