Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

19 files changed, 335 insertions, 71 deletions

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index f2c9687..ba86eea 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -27,7 +27,10 @@
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_DCU_ADDR			(CONFIG_SYS_IMMR + 0x01ce0000)
+#define CONFIG_SYS_LS102XA_USB1_ADDR \
+	(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)
 
+#define CONFIG_SYS_LS102XA_USB1_OFFSET		0x07600000
 #define CONFIG_SYS_TSEC1_OFFSET			0x01d10000
 #define CONFIG_SYS_TSEC2_OFFSET			0x01d50000
 #define CONFIG_SYS_TSEC3_OFFSET			0x01d90000
@@ -72,6 +75,10 @@
 
 #define DCU_LAYER_MAX_NUM			16
 
+#define QE_MURAM_SIZE          0x6000UL
+#define MAX_QE_RISC            1
+#define QE_NUM_OF_SNUM         28
+
 #define CONFIG_SYS_FSL_SRDS_1
 
 #ifdef CONFIG_LS102XA
@@ -80,6 +87,7 @@
 #define CONFIG_NUM_DDR_CONTROLLERS		1
 #define CONFIG_SYS_FSL_DDR_VER			FSL_DDR_VER_5_0
 #define CONFIG_SYS_FSL_SEC_COMPAT		5
+#define CONFIG_USB_MAX_CONTROLLER_COUNT		1
 #else
 #error SoC not defined
 #endif
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 7995fe2..b0c267c 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -95,8 +95,6 @@ struct ccsr_gur {
 	u32	sdhcpcr;
 };
 
-#define SCFG_SCFGREVCR_REV		0xffffffff
-#define SCFG_SCFGREVCR_NOREV		0
 #define SCFG_ETSECDMAMCR_LE_BD_FR	0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125	0x04000000
 #define SCFG_PIXCLKCR_PXCKEN		0x80000000
@@ -182,7 +180,7 @@ struct ccsr_scfg {
 	u32 etsecmcr;
 	u32 sdhciovserlcr;
 	u32 resv14[61];
-	u32 sparecr;
+	u32 sparecr[8];
 };
 
 /* Clocking */
@@ -448,6 +446,7 @@ struct ccsr_ddr {
 
 #define CCI400_CTRLORD_TERM_BARRIER	0x00000008
 #define CCI400_CTRLORD_EN_BARRIER	0
+#define CCI400_SHAORD_NON_SHAREABLE	0x00000002
 
 /* CCI-400 registers */
 struct ccsr_cci400 {
diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h
index c69d064..438f128 100644
--- a/arch/arm/include/asm/global_data.h
+++ b/arch/arm/include/asm/global_data.h
@@ -17,6 +17,14 @@ struct arch_global_data {
 #if defined(CONFIG_FSL_ESDHC)
 	u32 sdhc_clk;
 #endif
+
+#if defined(CONFIG_U_QE)
+	u32 qe_clk;
+	u32 brg_clk;
+	uint mp_alloc_base;
+	uint mp_alloc_top;
+#endif /* CONFIG_U_QE */
+
 #ifdef CONFIG_AT91FAMILY
 	/* "static data" needed by at91's clock.c */
 	unsigned long	cpu_clk_rate_hz;
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3a04a89..fe3eb06 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -9,6 +9,7 @@
 #include <linux/compiler.h>
 #include <asm/fsl_errata.h>
 #include <asm/processor.h>
+#include <fsl_usb.h>
 #include "fsl_corenet_serdes.h"
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004849
@@ -293,6 +294,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if (has_erratum_a007075())
 		puts("Work-around for Erratum A007075 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007798
+	if (has_erratum_a007798())
+		puts("Work-around for Erratum A007798 enabled\n");
+#endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_I2C_A004447
 	if ((SVR_SOC_VER(svr) == SVR_8548 && IS_SVR_REV(svr, 3, 1)) ||
 	    (SVR_REV(svr) <= CONFIG_SYS_FSL_A004447_SVR_REV))
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4c1774f..7860b40 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -678,6 +678,7 @@
 #define CONFIG_SYS_FSL_ERRATUM_A006379
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007798
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
diff --git a/arch/powerpc/include/asm/fsl_errata.h b/arch/powerpc/include/asm/fsl_errata.h
index 64da4bb..b9e2fb0 100644
--- a/arch/powerpc/include/asm/fsl_errata.h
+++ b/arch/powerpc/include/asm/fsl_errata.h
@@ -26,59 +26,4 @@ static inline bool has_erratum_a006379(void)
 	return false;
 }
 #endif
-
-#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
-static inline bool has_erratum_a006261(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P2041:
-	case SVR_P2040:
-		return IS_SVR_REV(svr, 1, 0) ||
-			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
-	case SVR_P3041:
-		return IS_SVR_REV(svr, 1, 0) ||
-			IS_SVR_REV(svr, 1, 1) ||
-			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
-	case SVR_P5010:
-	case SVR_P5020:
-	case SVR_P5021:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_T4240:
-	case SVR_T4160:
-	case SVR_T4080:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_T1040:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_T2080:
-	case SVR_T2081:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_P5040:
-		return IS_SVR_REV(svr, 1, 0);
-	}
-
-	return false;
-}
-#endif
-
-static inline bool has_erratum_a007075(void)
-{
-	u32 svr = get_svr();
-	u32 soc = SVR_SOC_VER(svr);
-
-	switch (soc) {
-	case SVR_B4860:
-	case SVR_B4420:
-		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
-	case SVR_P1010:
-		return IS_SVR_REV(svr, 1, 0);
-	case SVR_P4080:
-		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
-	}
-	return false;
-}
 #endif
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index c9c8eaa..5cb7570 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -90,7 +90,7 @@ static void show_eeprom(void)
 	/* EEPROM tag ID, either CCID or NXID */
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("ID: %c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
@@ -485,7 +485,7 @@ int mac_read_from_eeprom(void)
 
 #ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
-		be32_to_cpu(e.version));
+	       e.version);
 #else
 	printf("%c%c%c%c\n", e.id[0], e.id[1], e.id[2], e.id[3]);
 #endif
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index 7441a6b..0a7720a 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -17,6 +17,9 @@
 
 #include "../common/qixis.h"
 #include "ls1021aqds_qixis.h"
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -137,9 +140,8 @@ int board_early_init_f(void)
 	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
+	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
 #endif
 
 #ifdef CONFIG_FSL_IFC
@@ -230,6 +232,13 @@ int board_init(void)
 	/* Set CCI-400 control override register to
 	 * enable barrier transaction */
 	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
 
 	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 
@@ -237,6 +246,11 @@ int board_init(void)
 	fsl_serdes_init();
 	config_serdes_mux();
 #endif
+
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
 	return 0;
 }
 
diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c
index ee78769..3e8c37b 100644
--- a/board/freescale/ls1021atwr/ls1021atwr.c
+++ b/board/freescale/ls1021atwr/ls1021atwr.c
@@ -17,6 +17,10 @@
 #include <fsl_mdio.h>
 #include <tsec.h>
 #include <fsl_sec.h>
+#ifdef CONFIG_U_QE
+#include "../../../drivers/qe/qe.h"
+#endif
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -251,11 +255,8 @@ int board_early_init_f(void)
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_TSEC_ENET
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
 	out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
-	udelay(10);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 #ifdef CONFIG_FSL_IFC
@@ -263,9 +264,7 @@ int board_early_init_f(void)
 #endif
 
 #ifdef CONFIG_FSL_DCU_FB
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_REV);
 	out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
-	out_be32(&scfg->scfgrevcr, SCFG_SCFGREVCR_NOREV);
 #endif
 
 	return 0;
@@ -273,11 +272,25 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+
+	/*
+	 * Set CCI-400 Slave interface S0, S1, S2 Shareable Override Register
+	 * All transactions are treated as non-shareable
+	 */
+	out_le32(&cci->slave[0].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+	out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
+
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	fsl_serdes_init();
 	config_serdes_mux();
 #endif
 
+#ifdef CONFIG_U_QE
+	u_qe_init();
+#endif
+
 	return 0;
 }
 
diff --git a/drivers/Makefile b/drivers/Makefile
index 7683c61..5ef58c0 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,6 +16,7 @@ obj-y += twserial/
 obj-y += video/
 obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
+obj-$(CONFIG_U_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
diff --git a/drivers/qe/Makefile b/drivers/qe/Makefile
index 7f1bd06..8fa4866 100644
--- a/drivers/qe/Makefile
+++ b/drivers/qe/Makefile
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
 
-obj-y := qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
+obj-$(CONFIG_U_QE) += qe.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
diff --git a/drivers/qe/fdt.c b/drivers/qe/fdt.c
index d9a7d82..dfae4bf 100644
--- a/drivers/qe/fdt.c
+++ b/drivers/qe/fdt.c
@@ -12,6 +12,7 @@
 #include <fdt_support.h>
 #include "qe.h"
 
+#ifdef CONFIG_QE
 DECLARE_GLOBAL_DATA_PTR;
 
 /*
@@ -72,3 +73,4 @@ void ft_qe_setup(void *blob)
 		"clock-frequency", gd->arch.qe_clk / 2, 1);
 	fdt_fixup_qe_firmware(blob);
 }
+#endif
diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index 4358a91..bc94673 100644
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -40,6 +40,7 @@ void qe_issue_cmd(uint cmd, uint sbc, u8 mcn, u32 cmd_data)
 	return;
 }
 
+#ifdef CONFIG_QE
 uint qe_muram_alloc(uint size, uint align)
 {
 	uint	retloc;
@@ -70,6 +71,7 @@ uint qe_muram_alloc(uint size, uint align)
 
 	return retloc;
 }
+#endif
 
 void *qe_muram_addr(uint offset)
 {
@@ -180,6 +182,17 @@ void qe_init(uint qe_base)
 	qe_snums_init();
 }
 
+#ifdef CONFIG_U_QE
+void u_qe_init(void)
+{
+	uint qe_base = CONFIG_SYS_IMMR + 0x01400000; /* QE immr base */
+	qe_immr = (qe_map_t *)qe_base;
+
+	u_qe_upload_firmware((const void *)CONFIG_SYS_QE_FW_ADDR);
+	out_be32(&qe_immr->iram.iready, QE_IRAM_READY);
+}
+#endif
+
 void qe_reset(void)
 {
 	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
@@ -212,6 +225,7 @@ void qe_assign_page(uint snum, uint para_ram_base)
 
 #define BRG_CLK		(gd->arch.brg_clk)
 
+#ifdef CONFIG_QE
 int qe_set_brg(uint brg, uint rate)
 {
 	volatile uint	*bp;
@@ -239,6 +253,7 @@ int qe_set_brg(uint brg, uint rate)
 
 	return 0;
 }
+#endif
 
 /* Set ethernet MII clock master
 */
@@ -429,6 +444,131 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
 	return 0;
 }
 
+#ifdef CONFIG_U_QE
+/*
+ * Upload a microcode to the I-RAM at a specific address.
+ *
+ * See docs/README.qe_firmware for information on QE microcode uploading.
+ *
+ * Currently, only version 1 is supported, so the 'version' field must be
+ * set to 1.
+ *
+ * The SOC model and revision are not validated, they are only displayed for
+ * informational purposes.
+ *
+ * 'calc_size' is the calculated size, in bytes, of the firmware structure and
+ * all of the microcode structures, minus the CRC.
+ *
+ * 'length' is the size that the structure says it is, including the CRC.
+ */
+int u_qe_upload_firmware(const struct qe_firmware *firmware)
+{
+	unsigned int i;
+	unsigned int j;
+	u32 crc;
+	size_t calc_size = sizeof(struct qe_firmware);
+	size_t length;
+	const struct qe_header *hdr;
+#ifdef CONFIG_DEEP_SLEEP
+	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+#endif
+	if (!firmware) {
+		printf("Invalid address\n");
+		return -EINVAL;
+	}
+
+	hdr = &firmware->header;
+	length = be32_to_cpu(hdr->length);
+
+	/* Check the magic */
+	if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
+	    (hdr->magic[2] != 'F')) {
+		printf("Not a microcode\n");
+#ifdef CONFIG_DEEP_SLEEP
+		setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_QE_DISABLE);
+#endif
+		return -EPERM;
+	}
+
+	/* Check the version */
+	if (hdr->version != 1) {
+		printf("Unsupported version\n");
+		return -EPERM;
+	}
+
+	/* Validate some of the fields */
+	if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
+		printf("Invalid data\n");
+		return -EINVAL;
+	}
+
+	/* Validate the length and check if there's a CRC */
+	calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
+
+	for (i = 0; i < firmware->count; i++)
+		/*
+		 * For situations where the second RISC uses the same microcode
+		 * as the first, the 'code_offset' and 'count' fields will be
+		 * zero, so it's okay to add those.
+		 */
+		calc_size += sizeof(u32) *
+			be32_to_cpu(firmware->microcode[i].count);
+
+	/* Validate the length */
+	if (length != calc_size + sizeof(u32)) {
+		printf("Invalid length\n");
+		return -EPERM;
+	}
+
+	/*
+	 * Validate the CRC.  We would normally call crc32_no_comp(), but that
+	 * function isn't available unless you turn on JFFS support.
+	 */
+	crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
+	if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
+		printf("Firmware CRC is invalid\n");
+		return -EIO;
+	}
+
+	/*
+	 * If the microcode calls for it, split the I-RAM.
+	 */
+	if (!firmware->split) {
+		out_be16(&qe_immr->cp.cercr,
+			 in_be16(&qe_immr->cp.cercr) | QE_CP_CERCR_CIR);
+	}
+
+	if (firmware->soc.model)
+		printf("Firmware '%s' for %u V%u.%u\n",
+		       firmware->id, be16_to_cpu(firmware->soc.model),
+		       firmware->soc.major, firmware->soc.minor);
+	else
+		printf("Firmware '%s'\n", firmware->id);
+
+	/* Loop through each microcode. */
+	for (i = 0; i < firmware->count; i++) {
+		const struct qe_microcode *ucode = &firmware->microcode[i];
+
+		/* Upload a microcode if it's present */
+		if (ucode->code_offset)
+			qe_upload_microcode(firmware, ucode);
+
+		/* Program the traps for this processor */
+		for (j = 0; j < 16; j++) {
+			u32 trap = be32_to_cpu(ucode->traps[j]);
+
+			if (trap)
+				out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+		}
+
+		/* Enable traps */
+		out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+	}
+
+	return 0;
+}
+#endif
+
 struct qe_firmware_info *qe_get_firmware_info(void)
 {
 	return qe_firmware_uploaded ? &qe_firmware_info : NULL;
diff --git a/drivers/qe/qe.h b/drivers/qe/qe.h
index ebb7c5f..33878f8 100644
--- a/drivers/qe/qe.h
+++ b/drivers/qe/qe.h
@@ -285,4 +285,9 @@ void ft_qe_setup(void *blob);
 void qe_init(uint qe_base);
 void qe_reset(void);
 
+#ifdef CONFIG_U_QE
+void u_qe_init(void);
+int u_qe_upload_firmware(const struct qe_firmware *firmware);
+#endif
+
 #endif /* __QE_H__ */
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 45062e6..8f55464 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -14,7 +14,7 @@
 #include <asm/io.h>
 #include <usb/ehci-fsl.h>
 #include <hwconfig.h>
-#include <asm/fsl_errata.h>
+#include <fsl_usb.h>
 
 #include "ehci.h"
 
@@ -130,8 +130,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
 
 	in_le32(&ehci->usbmode);
 
-	if (SVR_SOC_VER(get_svr()) == SVR_T4240 &&
-	    IS_SVR_REV(get_svr(), 2, 0))
+	if (has_erratum_a007798())
 		set_txfifothresh(ehci, TXFIFOTHRESH);
 
 	return 0;
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index b19a60f..48e10ec 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -70,6 +70,11 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_HAS_SERDES
 
 #define CONFIG_FSL_CAAM			/* Enable CAAM */
+
+#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#define CONFIG_U_QE
+#endif
+
 /*
  * IFC Definitions
  */
@@ -110,6 +115,7 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
@@ -274,6 +280,23 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_GENERIC_MMC
 
 /*
+ * USB
+ */
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+/*
  * eTSEC
  */
 #define CONFIG_TSEC_ENET
@@ -332,6 +355,8 @@ unsigned long get_board_ddr_clk(void);
 
 #define CONFIG_BOOTDELAY		3
 
+#define CONFIG_SYS_QE_FW_ADDR     0x67f40000
+
 #define CONFIG_EXTRA_ENV_SETTINGS	\
 	"bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 	"fdt_high=0xcfffffff\0"		\
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index e98e102..3eac7ee 100644
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -50,6 +50,10 @@
 
 #define CONFIG_FSL_CAAM			/* Enable CAAM */
 
+#if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
+#define CONFIG_U_QE
+#endif
+
 /*
  * IFC Definitions
  */
@@ -95,6 +99,7 @@
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE_PHYS }
 
 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_WRITE_SWAPPED_DATA
 
 /* CPLD */
 
@@ -156,6 +161,17 @@
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 
+/* EEPROM */
+#ifndef CONFIG_SD_BOOT
+#define CONFIG_ID_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM		1
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	5
+#endif
+
 /*
  * MMC
  */
@@ -274,6 +290,8 @@
 
 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 
+#define CONFIG_SYS_QE_FW_ADDR     0x67f40000
+
 /*
  * Environment
  */
diff --git a/include/fsl_usb.h b/include/fsl_usb.h
index 1a6c9c1..e4902aa 100644
--- a/include/fsl_usb.h
+++ b/include/fsl_usb.h
@@ -85,4 +85,81 @@ struct ccsr_usb_phy {
 #define CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK 0x07
 #endif
 
+/* USB Erratum Checking code */
+#ifdef CONFIG_PPC
+static inline bool has_erratum_a006261(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P2041:
+	case SVR_P2040:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P3041:
+		return IS_SVR_REV(svr, 1, 0) ||
+			IS_SVR_REV(svr, 1, 1) ||
+			IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 2, 1);
+	case SVR_P5010:
+	case SVR_P5020:
+	case SVR_P5021:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T4240:
+	case SVR_T4160:
+	case SVR_T4080:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_T1040:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_T2080:
+	case SVR_T2081:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P5040:
+		return IS_SVR_REV(svr, 1, 0);
+	}
+
+	return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+	u32 svr = get_svr();
+	u32 soc = SVR_SOC_VER(svr);
+
+	switch (soc) {
+	case SVR_B4860:
+	case SVR_B4420:
+		return IS_SVR_REV(svr, 1, 0) || IS_SVR_REV(svr, 2, 0);
+	case SVR_P1010:
+		return IS_SVR_REV(svr, 1, 0);
+	case SVR_P4080:
+		return IS_SVR_REV(svr, 2, 0) || IS_SVR_REV(svr, 3, 0);
+	}
+	return false;
+}
+
+static inline bool has_erratum_a007798(void)
+{
+	return SVR_SOC_VER(get_svr()) == SVR_T4240 &&
+		IS_SVR_REV(get_svr(), 2, 0);
+}
+#else
+static inline bool has_erratum_a006261(void)
+{
+	return false;
+}
+
+static inline bool has_erratum_a007075(void)
+{
+	return false;
+}
+
+static inline bool has_erratum_a007798(void)
+{
+	return false;
+}
+
+#endif
 #endif /*_ASM_FSL_USB_H_ */
diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index dd77ad6..897018b 100644
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -163,6 +163,9 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR	0
+#elif defined(CONFIG_LS102XA)
+#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
+#define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
 
 /*