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| author | Stefan Agner <stefan@agner.ch> | 2016-05-05 13:42:45 -0700 |
|---|---|---|
| committer | fang hui <hui.fang@nxp.com> | 2017-01-19 14:48:35 +0800 |
| commit | 565648864c07221da689e9e26e0579ec8b600f8a (patch) | |
| tree | ee74f39d4b5de75f48790f1724c53fb93495a07f | |
| parent | eeff4e073c6408bbfdac1a1fb7e4a35b4e1bf85e (diff) | |
| download | u-boot-imx-565648864c07221da689e9e26e0579ec8b600f8a.zip u-boot-imx-565648864c07221da689e9e26e0579ec8b600f8a.tar.gz u-boot-imx-565648864c07221da689e9e26e0579ec8b600f8a.tar.bz2 | |
MA-9194 imx7d: fix ahb clock mux 1
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
(cherry picked from commit 8183b60202754d9d33ac1a2a68a5cc2cc4640fc6)
Change-Id: I5734f134a88249629dca0a956987a224f91744e9
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/clock_slice.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/mx7/clock_slice.c b/arch/arm/cpu/armv7/mx7/clock_slice.c index ad5d504..1665df9 100644 --- a/arch/arm/cpu/armv7/mx7/clock_slice.c +++ b/arch/arm/cpu/armv7/mx7/clock_slice.c @@ -55,7 +55,7 @@ static struct clk_root_map root_array[] = { PLL_ENET_MAIN_250M_CLK, PLL_AUDIO_MAIN_CLK} }, {AHB_CLK_ROOT, CCM_AHB_CHANNEL, - {OSC_24M_CLK, PLL_SYS_PFD2_135M_CLK, PLL_DRAM_MAIN_533M_CLK, + {OSC_24M_CLK, PLL_SYS_PFD2_270M_CLK, PLL_DRAM_MAIN_533M_CLK, PLL_SYS_PFD0_392M_CLK, PLL_ENET_MAIN_125M_CLK, PLL_USB_MAIN_480M_CLK, PLL_AUDIO_MAIN_CLK, PLL_VIDEO_MAIN_CLK} }, |