MA-9094 caam: enable 7d's caam

open caam's clock gate in 7d, add caam related configs.

Change-Id: I56351e3fcdbee96911d0c510990ba8fcd05c457f
Signed-off-by: Winter Wang <wente.wang@nxp.com>

5 files changed, 89 insertions, 70 deletions

diff --git a/arch/arm/include/asm/arch-mx7/crm_regs.h b/arch/arm/include/asm/arch-mx7/crm_regs.h
index 8a68a39..96c1d84 100644
--- a/arch/arm/include/asm/arch-mx7/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx7/crm_regs.h
@@ -2000,29 +2000,38 @@ struct mxc_ccm_anatop_reg {
 #define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR(x) (((uint32_t)(((uint32_t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_T_MUX_ADDR_MASK)
 
 
-#define CCM_GPR(i)		(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i))
-#define CCM_OBSERVE(i)		(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i))
-#define CCM_SCTRL(i)		(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i))
-#define CCM_CCGR(i)		(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i))
-#define CCM_ROOT_TARGET(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
-
-#define CCM_GPR_SET(i)		(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
-#define CCM_OBSERVE_SET(i)	(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
-#define CCM_SCTRL_SET(i)	(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
-#define CCM_CCGR_SET(i)		(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
-#define CCM_ROOT_TARGET_SET(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
-
-#define CCM_GPR_CLR(i)		(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
-#define CCM_OBSERVE_CLR(i)	(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
-#define CCM_SCTRL_CLR(i)	(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
-#define CCM_CCGR_CLR(i)		(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
-#define CCM_ROOT_TARGET_CLR(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
-
-#define CCM_GPR_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
-#define CCM_OBSERVE_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
-#define CCM_SCTRL_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
-#define CCM_CCGR_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
-#define CCM_ROOT_TARGET_TOGGLE(i)	(CCM_BASE_ADDRESS + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
+#define MXC_CCM_CCGR36_CAAM_DOMAIN3_OFFSET			12
+#define MXC_CCM_CCGR36_CAAM_DOMAIN3_MASK			(3 << MXC_CCM_CCGR36_CAAM_DOMAIN3_OFFSET)
+#define MXC_CCM_CCGR36_CAAM_DOMAIN2_OFFSET			8
+#define MXC_CCM_CCGR36_CAAM_DOMAIN2_MASK			(3 << MXC_CCM_CCGR36_CAAM_DOMAIN2_OFFSET)
+#define MXC_CCM_CCGR36_CAAM_DOMAIN1_OFFSET			4
+#define MXC_CCM_CCGR36_CAAM_DOMAIN1_MASK			(3 << MXC_CCM_CCGR36_CAAM_DOMAIN1_OFFSET)
+#define MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET			0
+#define MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK			(3 << MXC_CCM_CCGR36_CAAM_DOMAIN0_OFFSET)
+
+#define CCM_GPR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i))
+#define CCM_OBSERVE(i)		(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i))
+#define CCM_SCTRL(i)		(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i))
+#define CCM_CCGR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i))
+#define CCM_ROOT_TARGET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i))
+
+#define CCM_GPR_SET(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_OBSERVE_SET(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 4)
+#define CCM_SCTRL_SET(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 4)
+#define CCM_CCGR_SET(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 4)
+#define CCM_ROOT_TARGET_SET(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 4)
+
+#define CCM_GPR_CLR(i)		(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_OBSERVE_CLR(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 8)
+#define CCM_SCTRL_CLR(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 8)
+#define CCM_CCGR_CLR(i)		(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 8)
+#define CCM_ROOT_TARGET_CLR(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 8)
+
+#define CCM_GPR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_GPR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_OBSERVE_TOGGLE(i)	(CCM_BASE_ADDR + CCM_OBSERVE0_OFFSET + 0x10 * (i) + 12)
+#define CCM_SCTRL_TOGGLE(i)	(CCM_BASE_ADDR + CCM_SCTRL0_OFFSET + 0x10 * (i) + 12)
+#define CCM_CCGR_TOGGLE(i)	(CCM_BASE_ADDR + CCM_CCGR0_OFFSET + 0x10 * (i) + 12)
+#define CCM_ROOT_TARGET_TOGGLE(i)	(CCM_BASE_ADDR + CCM_ROOT0_TARGET_OFFSET + 0x80 * (i) + 12)
 
 #define HW_CCM_GPR_WR(i, v)		writel((v), CCM_GPR(i))
 #define HW_CCM_CCM_OBSERVE_WR(i, v)	writel((v), CCM_OBSERVE(i))
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index cf88831..79dfdbe 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -218,6 +218,10 @@
 
 #define CHIP_REV_1_0                 0x10
 #define CHIP_REV_1_1                 0x11
+
+#define CONFIG_SYS_FSL_SEC_ADDR         (CAAM_IPS_BASE_ADDR)
+#define CONFIG_SYS_FSL_JR0_ADDR         (CONFIG_SYS_FSL_SEC_ADDR  + 0x1000)
+
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
diff --git a/drivers/crypto/fsl_caam.c b/drivers/crypto/fsl_caam.c
index ebba87c..9f0ae10 100755
--- a/drivers/crypto/fsl_caam.c
+++ b/drivers/crypto/fsl_caam.c
@@ -369,16 +369,21 @@ uint32_t caam_hwrng(uint8_t *output_ptr, uint32_t output_len) {
  */
 void caam_open(void)
 {
-	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	uint32_t temp_reg;
-	//uint32_t addr;
 
     /* switch on the clock */
+#if defined(CONFIG_MX6)
+	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	//uint32_t addr;
+
 	temp_reg = __raw_readl(&mxc_ccm->CCGR0);
 	temp_reg |= MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK |
 		MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 		MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK;
 	__raw_writel(temp_reg, &mxc_ccm->CCGR0);
+#elif defined(CONFIG_MX7)
+	HW_CCM_CCGR_SET(36,	MXC_CCM_CCGR36_CAAM_DOMAIN0_MASK);
+#endif
 
     /* MID for CAAM - already done by HAB in ROM during preconfigure,
      * That is JROWN for JR0/1 = 1 (TZ, Secure World, ARM)
diff --git a/drivers/crypto/fsl_caam_internal.h b/drivers/crypto/fsl_caam_internal.h
index 755cad8..363cfdd 100644
--- a/drivers/crypto/fsl_caam_internal.h
+++ b/drivers/crypto/fsl_caam_internal.h
@@ -40,55 +40,55 @@
 #define SEC_MEM_PAGE3       (CAAM_SEC_RAM_START_ADDR + 0x3000)
 
 /* Configuration and special key registers */
-#define CAAM_MCFGR          CAAM_BASE_ADDR + 0x0004
-#define CAAM_SCFGR          CAAM_BASE_ADDR + 0x000c
-#define CAAM_JR0MIDR        CAAM_BASE_ADDR + 0x0010
-#define CAAM_JR1MIDR        CAAM_BASE_ADDR + 0x0018
-#define CAAM_DECORR         CAAM_BASE_ADDR + 0x009c
-#define CAAM_DECO0MID       CAAM_BASE_ADDR + 0x00a0
-#define CAAM_DAR            CAAM_BASE_ADDR + 0x0120
-#define CAAM_DRR            CAAM_BASE_ADDR + 0x0124
-#define CAAM_JDKEKR         CAAM_BASE_ADDR + 0x0400
-#define CAAM_TDKEKR         CAAM_BASE_ADDR + 0x0420
-#define CAAM_TDSKR          CAAM_BASE_ADDR + 0x0440
-#define CAAM_SKNR           CAAM_BASE_ADDR + 0x04e0
-#define CAAM_SMSTA          CAAM_BASE_ADDR + 0x0FB4
-#define CAAM_STA            CAAM_BASE_ADDR + 0x0FD4
-#define CAAM_SMPO_0         CAAM_BASE_ADDR + 0x1FBC
+#define CAAM_MCFGR          CONFIG_SYS_FSL_SEC_ADDR + 0x0004
+#define CAAM_SCFGR          CONFIG_SYS_FSL_SEC_ADDR + 0x000c
+#define CAAM_JR0MIDR        CONFIG_SYS_FSL_SEC_ADDR + 0x0010
+#define CAAM_JR1MIDR        CONFIG_SYS_FSL_SEC_ADDR + 0x0018
+#define CAAM_DECORR         CONFIG_SYS_FSL_SEC_ADDR + 0x009c
+#define CAAM_DECO0MID       CONFIG_SYS_FSL_SEC_ADDR + 0x00a0
+#define CAAM_DAR            CONFIG_SYS_FSL_SEC_ADDR + 0x0120
+#define CAAM_DRR            CONFIG_SYS_FSL_SEC_ADDR + 0x0124
+#define CAAM_JDKEKR         CONFIG_SYS_FSL_SEC_ADDR + 0x0400
+#define CAAM_TDKEKR         CONFIG_SYS_FSL_SEC_ADDR + 0x0420
+#define CAAM_TDSKR          CONFIG_SYS_FSL_SEC_ADDR + 0x0440
+#define CAAM_SKNR           CONFIG_SYS_FSL_SEC_ADDR + 0x04e0
+#define CAAM_SMSTA          CONFIG_SYS_FSL_SEC_ADDR + 0x0FB4
+#define CAAM_STA            CONFIG_SYS_FSL_SEC_ADDR + 0x0FD4
+#define CAAM_SMPO_0         CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC
 
 /* RNG registers */
-#define CAAM_RTMCTL         CAAM_BASE_ADDR + 0x0600
-#define CAAM_RTSDCTL        CAAM_BASE_ADDR + 0x0610
-#define CAAM_RTFRQMIN       CAAM_BASE_ADDR + 0x0618
-#define CAAM_RTFRQMAX       CAAM_BASE_ADDR + 0x061C
-#define CAAM_RTSTATUS		CAAM_BASE_ADDR + 0x063C
-#define CAAM_RDSTA          CAAM_BASE_ADDR + 0x06C0
+#define CAAM_RTMCTL         CONFIG_SYS_FSL_SEC_ADDR + 0x0600
+#define CAAM_RTSDCTL        CONFIG_SYS_FSL_SEC_ADDR + 0x0610
+#define CAAM_RTFRQMIN       CONFIG_SYS_FSL_SEC_ADDR + 0x0618
+#define CAAM_RTFRQMAX       CONFIG_SYS_FSL_SEC_ADDR + 0x061C
+#define CAAM_RTSTATUS       CONFIG_SYS_FSL_SEC_ADDR + 0x063C
+#define CAAM_RDSTA          CONFIG_SYS_FSL_SEC_ADDR + 0x06C0
 
 /* Job Ring 0 registers */
-#define CAAM_IRBAR0         CAAM_BASE_ADDR + 0x1004
-#define CAAM_IRSR0          CAAM_BASE_ADDR + 0x100c
-#define CAAM_IRSAR0         CAAM_BASE_ADDR + 0x1014
-#define CAAM_IRJAR0         CAAM_BASE_ADDR + 0x101c
-#define CAAM_ORBAR0         CAAM_BASE_ADDR + 0x1024
-#define CAAM_ORSR0          CAAM_BASE_ADDR + 0x102c
-#define CAAM_ORJRR0         CAAM_BASE_ADDR + 0x1034
-#define CAAM_ORSFR0         CAAM_BASE_ADDR + 0x103c
-#define CAAM_JRSTAR0        CAAM_BASE_ADDR + 0x1044
-#define CAAM_JRINTR0        CAAM_BASE_ADDR + 0x104c
-#define CAAM_JRCFGR0_MS     CAAM_BASE_ADDR + 0x1050
-#define CAAM_JRCFGR0_LS     CAAM_BASE_ADDR + 0x1054
-#define CAAM_IRRIR0         CAAM_BASE_ADDR + 0x105c
-#define CAAM_ORWIR0         CAAM_BASE_ADDR + 0x1064
-#define CAAM_JRCR0          CAAM_BASE_ADDR + 0x106c
-#define CAAM_SMCJR0         CAAM_BASE_ADDR + 0x10f4
-#define CAAM_SMCSJR0        CAAM_BASE_ADDR + 0x10fc
-#define CAAM_SMAPJR0(y)     (CAAM_BASE_ADDR + 0x1104 + y*16)
-#define CAAM_SMAG2JR0(y)    (CAAM_BASE_ADDR + 0x1108 + y*16)
-#define CAAM_SMAG1JR0(y)    (CAAM_BASE_ADDR + 0x110C + y*16)
-#define CAAM_SMAPJR0_PRTN1  CAAM_BASE_ADDR + 0x1114
-#define CAAM_SMAG2JR0_PRTN1 CAAM_BASE_ADDR + 0x1118
-#define CAAM_SMAG1JR0_PRTN1 CAAM_BASE_ADDR + 0x111c
-#define CAAM_SMPO           CAAM_BASE_ADDR + 0x1fbc
+#define CAAM_IRBAR0         CONFIG_SYS_FSL_SEC_ADDR + 0x1004
+#define CAAM_IRSR0          CONFIG_SYS_FSL_SEC_ADDR + 0x100c
+#define CAAM_IRSAR0         CONFIG_SYS_FSL_SEC_ADDR + 0x1014
+#define CAAM_IRJAR0         CONFIG_SYS_FSL_SEC_ADDR + 0x101c
+#define CAAM_ORBAR0         CONFIG_SYS_FSL_SEC_ADDR + 0x1024
+#define CAAM_ORSR0          CONFIG_SYS_FSL_SEC_ADDR + 0x102c
+#define CAAM_ORJRR0         CONFIG_SYS_FSL_SEC_ADDR + 0x1034
+#define CAAM_ORSFR0         CONFIG_SYS_FSL_SEC_ADDR + 0x103c
+#define CAAM_JRSTAR0        CONFIG_SYS_FSL_SEC_ADDR + 0x1044
+#define CAAM_JRINTR0        CONFIG_SYS_FSL_SEC_ADDR + 0x104c
+#define CAAM_JRCFGR0_MS     CONFIG_SYS_FSL_SEC_ADDR + 0x1050
+#define CAAM_JRCFGR0_LS     CONFIG_SYS_FSL_SEC_ADDR + 0x1054
+#define CAAM_IRRIR0         CONFIG_SYS_FSL_SEC_ADDR + 0x105c
+#define CAAM_ORWIR0         CONFIG_SYS_FSL_SEC_ADDR + 0x1064
+#define CAAM_JRCR0          CONFIG_SYS_FSL_SEC_ADDR + 0x106c
+#define CAAM_SMCJR0         CONFIG_SYS_FSL_SEC_ADDR + 0x10f4
+#define CAAM_SMCSJR0        CONFIG_SYS_FSL_SEC_ADDR + 0x10fc
+#define CAAM_SMAPJR0(y)     (CONFIG_SYS_FSL_SEC_ADDR + 0x1104 + y*16)
+#define CAAM_SMAG2JR0(y)    (CONFIG_SYS_FSL_SEC_ADDR + 0x1108 + y*16)
+#define CAAM_SMAG1JR0(y)    (CONFIG_SYS_FSL_SEC_ADDR + 0x110C + y*16)
+#define CAAM_SMAPJR0_PRTN1  CONFIG_SYS_FSL_SEC_ADDR + 0x1114
+#define CAAM_SMAG2JR0_PRTN1 CONFIG_SYS_FSL_SEC_ADDR + 0x1118
+#define CAAM_SMAG1JR0_PRTN1 CONFIG_SYS_FSL_SEC_ADDR + 0x111c
+#define CAAM_SMPO           CONFIG_SYS_FSL_SEC_ADDR + 0x1fbc
 
 #define JRCFG_LS_IMSK       0x00000001      /* Interrupt Mask */
 #define JR_MID              2               /* Matches ROM configuration */
diff --git a/include/configs/mx7dsabresdbrillo.h b/include/configs/mx7dsabresdbrillo.h
index 9ebb05f..0d939f9 100644
--- a/include/configs/mx7dsabresdbrillo.h
+++ b/include/configs/mx7dsabresdbrillo.h
@@ -20,6 +20,7 @@
 #endif
 #endif
 
+#define CONFIG_FSL_CAAM_KB
 #define CONFIG_SHA1
 #define CONFIG_SHA256