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authorRupjyoti Sarmah <rsarmah@amcc.com>2009-09-21 11:26:19 -0700
committerStefan Roese <sr@denx.de>2009-09-23 15:46:08 +0200
commitfcdb36b85ac033c09a9762a0a14808f7cb2ed54c (patch)
tree17b4341af26367ecfe4a8f3f81c63776d765fce5
parent91d599044caac4a8c228115b16cf3b073f902080 (diff)
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ppc4xx: Fix PCIE PLL lock on 440SPe Yucca board
u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
-rw-r--r--cpu/ppc4xx/4xx_pcie.c23
1 files changed, 15 insertions, 8 deletions
diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 07fbb0e..e880c28 100644
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -374,28 +374,35 @@ int ppc4xx_init_pcie(void)
/* Set PLL clock receiver to LVPECL */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28);
- if (check_error())
+ if (check_error()) {
+ printf("ERROR: failed to set PCIe reference clock receiver --"
+ "PESDR0_PLLLCT1 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT1));
+
return -1;
+ }
+
+ /* Did resistance calibration work? */
+ if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) {
+ printf("ERROR: PCIe resistance calibration failed --"
+ "PESDR0_PLLLCT2 = 0x%08x\n", SDR_READ(PESDR0_PLLLCT2));
- if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000))
- {
- printf("PCIE: PESDR_PLLCT2 resistance calibration failed (0x%08x)\n",
- SDR_READ(PESDR0_PLLLCT2));
return -1;
}
/* De-assert reset of PCIe PLL, wait for lock */
SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24));
- udelay(3);
+ udelay(300); /* 300 uS is maximum time lock should take */
while (time_out) {
if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) {
time_out--;
- udelay(1);
+ udelay(20); /* Wait 20 uS more if needed */
} else
break;
}
if (!time_out) {
- printf("PCIE: VCO output not locked\n");
+ printf("ERROR: PCIe PLL VCO output not locked to ref clock --"
+ "PESDR0_PLLLCTS=0x%08x\n", SDR_READ(PESDR0_PLLLCT3));
+
return -1;
}
return 0;